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Simulators >> AMS Simulators >> ams designer starts and then hangs
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Message started by southofthebay on Jan 10^th, 2007, 6:12pm

Title: ams designer starts and then hangs
Post by southofthebay on Jan 10^th, 2007, 6:12pm

Hi all,

I am trying to run an AMS Designer simulation involving pure verilog rtl and verilogAMS converted from a PLL schematic.

I have a weird problem: when I try to reset the charge pump inside of the PLL (either with a digital control pin or with a vpwl inside the schematic), the simulator hangs. I hold reset on at t=0 and then release it sometime later t>0. The simulation starts fine and runs until reset is released. It then runs for several hundred ns more. The simulation step size then decreases where it becomes 1 fs and then hangs.

Do any of you have some suggestions as to what is causing the problems?

Thanks,
southofthebay

Title: Re: ams designer starts and then hangs
Post by jbdavid on Jan 22^nd, 2007, 8:11pm

first thing I'd consider is:
Look to see if you have used a non-discrete variable as the argument to a "transition" statement..

Since it sounds like you are using schematic (analog) + digital and no Verilog-AMS models other than the
connect modules, I'd double check those too... Are you using the right set? are they the latest version?

Are you using a recent IUS release? (ie 5.7 or 5.8 or higher?)

ALSO check the convergence settings. (after all THAT's whats getting bogged down.

jbd