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Modeling >> Semiconductor Devices >> Laser diode verilog-a Model(QWLD )
https://designers-guide.org/forum/YaBB.pl?num=1170411915

Message started by micro.duke on Feb 2^nd, 2007, 2:25am

Title: Laser diode verilog-a Model(QWLD )
Post by micro.duke on Feb 2^nd, 2007, 2:25am

Who can wirte a laser diode verilog-a Model?

I have a laser diode source code in pspice format.

Who can convert it to verilog-a or hspice?

help me .

Thanks.

Title: Re: Laser diode verilog-a Model(QWLD )
Post by Geoffrey_Coram on Feb 2^nd, 2007, 5:04am

It's not that hard, you can probably do it yourself. How long is the source code?

Title: Re: Laser diode verilog-a Model(QWLD )
Post by mg777 on Feb 2^nd, 2007, 8:06am

http://www.photonics.ee.ethz.ch/publications/MOT_Lett_Jungo_2003.pdf

is an excellent paper on the subject. It deals with VCSEL's, but the rate equation methodology will work for long cavity lasers as well. In particular note that a fixed integration time step has been used (see Sec. 4). Beam profiles are obtained too, so this is pretty powerful stuff.

M.G.Rajan
www.eecalc.com

Title: Re: Laser diode verilog-a Model(QWLD )
Post by micro.duke on Feb 2^nd, 2007, 7:39pm

Thanks.

The source code is not long.I try convert it to verilog-a or hspice format.But I'm not succeed. :'(

On the other hand. It is a circuit model for qwld.It's not 2D/3D model.I'm not care 2D/3D model.

Because I'm designing a Laser-diode drivers for SDH/SONET System(155Mbps~1250Mbps or 2.5Gbps).So I simulating the drivers with the QWLD Model.

Who Can convert it to verilog-a or hspice format.

Or who make a model for me ?

Thanks.

Title: Re: Laser diode verilog-a Model(QWLD )
Post by Geoffrey_Coram on Feb 5^th, 2007, 5:51am

micro.duke wrote on Feb 2^nd, 2007, 7:39pm:

Who Can convert it to verilog-a or hspice format.

I'm fairly sure I *could* do it, but it would take me a good hour at least, and then I don't have PSpice to verify it ...

Why don't you post your best effort so far, and see if we can help you debug it.

Title: Re: Laser diode verilog-a Model(QWLD )
Post by micro.duke on Feb 5^th, 2007, 5:49pm

Thanks a lot.

In first. I do try convert it to hspice format. but somthing(eg. 'func' ,The 'G' device is 2 port device in pspice,But in hspice it is 4 port device. etc.) can not translate it.

About 15 days ago. I known the verilog-a language.So I do not try conver it to verilog-a format.
But I know the language can do it.

If you have interest it.You can download Pspice simulator & pspice netlist form here:

http://www.ee.tsinghua.edu.cn/~zhangyejin/oeic.rar
(11M sn:123456 site:http://www.ee.tsinghua.edu.cn/~zhangyejin/oeic.htm Maybe you must down 3 dll file form http://www.dll-files.com/)

Thank you very much.

Title: Re: Laser diode verilog-a Model(QWLD )
Post by Geoffrey_Coram on Feb 6^th, 2007, 6:46am

micro.duke wrote on Feb 5^th, 2007, 5:49pm:

In first. I do try convert it to hspice format. but somthing(eg. 'func' ,The 'G' device is 2 port device in pspice,But in hspice it is 4 port device. etc.) can not translate it.

I'veseen an HSpice example that has

Gdio 5 0 CUR='1e-15*V(5)'

which would be a 2-port device.

Title: Re: Laser diode verilog-a Model(QWLD )
Post by micro.duke on Feb 6^th, 2007, 7:59pm

Geoffrey_Coram wrote on Feb 6^th, 2007, 6:46am:

I'veseen an HSpice example that has

Gdio 5 0 CUR='1e-15*V(5)'

which would be a 2-port device.

So Counld you tell me what's it means?

Quote:

HSPICE/SPICE™ Interface and SPICE™
2G.6 Reference Manual
Product Version 5.1.41
June 2004

Page 85:

Voltage-Controlled Current Sources

General form:

GXXXXXXX N+ N- <POLY(ND)>NC1+NC1- ... P0 <P1 ...> <IC=. .>

Examples:
G1 1 0 5 3 0 0.1M
GR 17 3 17 3 0 1M 1.5M IC=2V
GMLT 23 17 POLY(2) 3 5 1 2 0 1M 17M 3.5U IC=2.5,1.3

N+ and N- are the positive and negative nodes, respectively. Current flow is from the positive
node, through the source, to the negative node. POLY(ND) only has to be specified if the
source is multi-dimensional (one-dimensional is the default). If specified, ND is the number of
dimensions, which must be positive. NC1+, NC1-,. . . are the positive and negative controlling
nodes, respectively. One pair of nodes must be specified for each dimension. P0, P1, P2, . .
., Pn are the polynomial coefficients. The (optional) initial condition is the initial guess at the
value(s) of the controlling voltage(s). If not specified, 0.0 is assumed. The polynomial
specifies the source current as a function of the controlling voltage(s). The second example
above describes a current source with value
I = 1E-3*V(17,3)+1.5E-3*V(17,3)**2)

Title: Re: Laser diode verilog-a Model(QWLD )
Post by Geoffrey_Coram on Feb 7^th, 2007, 7:08am

micro.duke wrote on Feb 6^th, 2007, 7:59pm:

Geoffrey_Coram wrote on Feb 6^th, 2007, 6:46am:

I'veseen an HSpice example that has

Gdio 5 0 CUR='1e-15*V(5)'

which would be a 2-port device.

So Counld you tell me what's it means?

It's a voltage-dependent current source; the current is supplied across nodes 5 and 0 and has a value given by the expression. My understanding is that you can put any expression of voltages (and currents?) in the CUR='' expression; in this case, the current is 1e-15 * the voltage on 5. One could also have CUR='1e-15*(exp(V(5,0)/0.026) -1.0)' to get a diode, and I think the V() reference doesn't have to refer to the same nodes that the current is supplied across.

Title: Re: Laser diode verilog-a Model(QWLD )
Post by micro.duke on Feb 8^th, 2007, 12:33am

OK.

If you are right.We can simulate the circuit.

Quote:

V01 6 0 1
Gdio 5 0 CUR='1e-15*V(5)'
R1 5 6 10
R2 6 0 1m

.OPTION runlvl=5
.OPTION POST=1
.OPTION POST_VERSION=9601
.OPTION INGOLD=1
.OPTION ACCURATE=1
.OPTION PROBE
.PROBE I(R1) V(5) V(R1)
.TRAN 1n 2u

.end

But I do it & have no result. :(

Maybe the circuit is error. ;)

Thanks.

Title: Re: Laser diode verilog-a Model(QWLD )
Post by Geoffrey_Coram on Feb 8^th, 2007, 11:11am

The Gdio current is 1e-15 times the voltage; this is absolutely tiny. Change it to 1e3 -- or make it a real diode, with an exp().

Title: Re: Laser diode verilog-a Model(QWLD )
Post by micro.duke on Feb 11^th, 2007, 8:44pm

OK.
I will try do it.

Thanks.