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Design Languages >> VHDL-AMS >> 'RAMP attribute in Cadence
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Message started by wprodanov on Feb 22^nd, 2007, 8:29am

Title: 'RAMP attribute in Cadence
Post by wprodanov on Feb 22^nd, 2007, 8:29am

Hello mates,

I'm using ncsim simulator (Cadence IUS 5.7). When using 'RAMP attribute to define a voltage quantity from a voltage signal, sometimes the resulting quantity doesn't varies linearly as expected. Instead, it is "updated" abruptly only at the instant when the variation should finished. Anyone have seen the same behavior? Any idea how to work around?

thanks
william

Title: Re: 'RAMP attribute in Cadence
Post by abhi_kolpekwar on Feb 22^nd, 2007, 1:32pm

Hi,

Are you setting a "break" on the signal that is used in the RAMP attribute?

Title: Re: 'RAMP attribute in Cadence
Post by wprodanov on Feb 23^rd, 2007, 2:24am

According to the language standards the use of break is not necessary when using 'RAMP, isn't it? Anyway, thanks for replying and I'll check the difference using or not using it.

Title: Re: 'RAMP attribute in Cadence
Post by alinalin19832007 on May 29^th, 2008, 1:14pm

Maybe the step time for the analog solver it is not constant