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Design >> High-Power Design >> Noise problem in a buck DCDC
https://designers-guide.org/forum/YaBB.pl?num=1173797623

Message started by Matthieu on Mar 13^th, 2007, 7:53am

Title: Noise problem in a buck DCDC
Post by Matthieu on Mar 13^th, 2007, 7:53am

Hi all,

I am currently fixing (Designer have left the company and that the first time I am working on a Buck dcdc) an integrated buck DCDC converter (voltage mode). Silicon DCDC oscillates in some cases. I have been able to reproduce thoses oscillations in simulations but I don't know the solution to apply (I can do a full fix). The problem on silicon is ground noise inside the circuit due to parasitic resistance on ground (DCDC can just operates in CCM mode). When switching from NMOS to PMOS, internal ground goes up or down of ~10-20 mV. This is critical at the level of error amplifier:

1- Internal ground goes down of 20mV.
2- Bandgap voltage goes down following internal ground.
3- Feedback voltage remains constant because it is referenced to outside ground.
4- Difference between Feedback and bandgap generates error to abruptly reach 0.
5- Error cross ramp at this instant and makes DCDC switch.

As anyone experienced same types of problems?

I have tried to sample/hold both bandgap and feedback but it generates too much lag in the loop. Do you have any idea how such problem can be solved?

Thank you

Matthieu

Title: Re: Noise problem in a buck DCDC
Post by Matthieu on Mar 16^th, 2007, 2:00am

For information, I think I have found the solution by limiting error amplifier bandwidth (cut-off Fs/2 in closed loop).