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Design Languages >> VHDL-AMS >> sigma delta ADC in SMASH
https://designers-guide.org/forum/YaBB.pl?num=1174811994

Message started by seamus on Mar 25^th, 2007, 1:39am

Title: sigma delta ADC in SMASH
Post by seamus on Mar 25^th, 2007, 1:39am

hi everyone,
im undergraduate student and hving some questions related sigma delta modulator in dolphin SMASH. The coding shown below was having some errors which im not able to solve:

>>> VHDL
----------------------------------------------------------------
/* combine */
----------------------------------------------------------------
LIBRARY IEEE;
use IEEE.MATH_REAL.all;
use IEEE.STD_LOGIC_1164.all;
use IEEE.ELECTRICAL_SYSTEMS.all;
USE work.all;

entity sdm_1 is
PORT(
TERMINAL vin : ELECTRICAL;
SIGNAL clk : IN STD_LOGIC;
SIGNAL op : OUT STD_LOGIC);
END sdm_1;

ARCHITECTURE simple OF sdm_1 IS
TERMINAL adder2o : ELECTRICAL;
TERMINAL intero : ELECTRICAL;
SIGNAL Qo : STD_LOGIC;
TERMINAL DACo : ELECTRICAL;
BEGIN

adder_1 : entity ADDER(simple)
GENERIC MAP(A => 1.0,B => -1.0)
PORT MAP(ip1 => vin,ip2 => DACo,op =>adder2o);

inter_1 : entity inter(simple)
PORT MAP(ip => adder2o,op =>intero);

Q : entity quantizer(simple)
GENERIC MAP(threshod => 0.0)
PORT MAP(clk => clk,ip => intero,op => Qo);

DAC_1 : entity DAC(simple)
GENERIC MAP(mx => 5.0,mn => -5.0)
PORT MAP(ip => Qo,op => DACo);
op <= Qo;

END simple;
------------------------------------------------------------
library IEEE;
use ieee.math_real.all;
use ieee.std_logic_1164.all;
use IEEE.ELECTRICAL_SYSTEMS.all;
USE work.all;

entity top_circuit is
end top_circuit;

architecture test of top_circuit is
terminal A : electrical;
quantity xin across iin through A to electrical_ref;
signal op : std_logic;
signal clk : std_logic;

begin
m_sdm3 : entity sdm_1(simple)
port map(vin => A,clk =>clk,op => op);
xin == 5.0*sin(math_2_pi*1.0e6*NOW);
process
begin
clk <= '1';
wait for 500 ps;
clk <= '0';
wait for 500 ps;
end process;

end test;

--------------------------------------------------------------------------------------------------------
integrator sub-block
--7. Integrator --
--Used as an integrator for Sigma-Delta Converters --
----------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.MATH_REAL.ALL;
use ieee.math_complex.all;
USE IEEE.ELECTRICAL_SYSTEMS.ALL;
use IEEE.STD_LOGIC_signed.all;
use IEEE.STD_LOGIC_arith.all;
ENTITY inter is
PORT(TERMINAL ip : ELECTRICAL;
TERMINAL op : ELECTRICAL);
END inter;

ARCHITECTURE simple OF inter IS

QUANTITY vop ACROSS iop THROUGH op TO ELECTRICAL_REF;
QUANTITY vip ACROSS ip TO ELECTRICAL_REF;

BEGIN

vop == vip'integ;
END simple;
----------------------------------------------------------------------------------------------

--PAT file--

.VHDL SET KIND=AMS
.VHDL elaborate entity=top_circuit unit=test

.VHDL compile library=work source=adder.vhd
.VHDL compile library=work source=dac.vhd
.VHDL compile library=work source=inter.vhd
.VHDL compile library=work source=quantizer.vhd

--error found--
Compiling Entity Declaration INTER
Compiling Architecture SIMPLE of INTER
Compiling Entity Declaration SDM_1
Compiling Architecture SIMPLE of SDM_1
Compiling Entity Declaration TOP_CIRCUIT
Compiling Architecture TEST of TOP_CIRCUIT
Creating library file: libwork_inter.a

Creating library file: libwork_sdm_1.a

Creating library file: libwork_top_circuit.a

work_inter_simple.cpp: In member function `short int WORK::INTER_SIMPLE::AmsBim(long int, TRANS_PARAM_BIM*)':

work_inter_simple.cpp:390: error: `VIP_INTEG_INTEG_q6_row' was not declared in this scope

ERROR: unable to compile work_inter_simple.cpp
Creating library file: libwork_sdm_1_simple.a

Creating library file: libwork_top_circuit_test.a

im so frustrated and cant solve the problem, can anyone help me? thx a million... :-[

regards, seamus