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Other CAD Tools >> Entry Tools >> Layout Snap Spacing
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Message started by Faisal on May 7^th, 2007, 12:43am

Title: Layout Snap Spacing
Post by Faisal on May 7^th, 2007, 12:43am

In the Virtuso, Display options, through Layout Snap Spacing, I can control the X, Y snap spacing. What are the trade-offs or issues if I choose a too small snap spacing e.g. 0.001

The defualt X, Y snap spacing is at 0.5 but with this option I cannot place my PCELLS on the grid. I need the "RULER" for the layout rules etc and the RULER only works on the grid.

I am working on 0.18um. Has this something to do with the technology node?

Title: Re: Layout Snap Spacing
Post by Faisal on May 7^th, 2007, 1:29am

I get the following warning message, when I set my snapSpacing to 0.001 in Virtuso Display Options

*WARNING* 'ySnapSpacing' is not a multiple of 'mfgGridResolution' (0.005).

Can anyone explain what is the significance of mfgGridResolution?

Title: Re: Layout Snap Spacing
Post by didac on May 7^th, 2007, 4:03am

This parameter is a foundry limitation, is their ability to place the masks on the wafer, if you make a smaller grid probably when you check the DRC of the layout you will find lots of errors about 'offgrid', if you don't correct this errors the foundry will refuse your fabrication order.

Title: Re: Layout Snap Spacing
Post by krishnap on May 7^th, 2007, 9:04pm

Usually process is done based on the MEBUS address unit. This is the minimum grid upon which process is possible.
Any resolution below this manufacturing will not be possible.
Also, Raster scanning method is used in fabrication based on this address unit.

Title: Re: Layout Snap Spacing
Post by Faisal on May 8^th, 2007, 2:56am

Thanks, so it means the minimum snapSpacing i can choose is 0.005, as my mfgGridResolution (defined by technology file) is 0.005 ??

Title: Re: Layout Snap Spacing
Post by didac on May 8^th, 2007, 2:59am

Yes, good luck with your layout.