The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Modeling >> Behavioral Models >> clocked comparator in verilog A
https://designers-guide.org/forum/YaBB.pl?num=1179148349

Message started by senyou78 on May 14^th, 2007, 6:12am

Title: clocked comparator in verilog A
Post by senyou78 on May 14^th, 2007, 6:12am

hi, I m looking for a good code of a clocked comparator (it s a part of designing first order delta-sigma modolator),wenn I simulate the comparator alone, is working fine,but wenn I implemented in the whole circuit I don´t get the result what i expected,I don´t know if my code is a good one.I use cadence and verilog A to implement my circuit .here is the code what I use:
// VerilogA for senna,comparateur, veriloga

`include "constants.vams"
`include "disciplines.vams"

module comparateur(inp, inn, Clk, vp,vn);
input inp, inn;
voltage inp, inn;

input Clk;
voltage Clk;

output vp,vn;
voltage vp,vn;

parameter real vth = 0.6;
parameter real dir = +1 from [-1:1] exclude 0;
branch(inp,inn) in;
real hold;

analog begin
@(cross((V(Clk)-vth), +1)) begin
if (V(in) > vth)
hold = 1.2;
else
hold = -1.2;
end
V(vp) <+ hold;
V(vn) <+ -hold;
end
endmodule
can somebody help me und give me a good code or recommendations? :(
best regard
senyou

Title: Re: clocked comparator in verilog A
Post by Eugene on May 14^th, 2007, 8:00am

Off hand I don't see any problem with your code. However, when I run into compatibility problems between behavioral and device level models, it is usually because the behavioral model does not have the correct common mode voltage. You may want to check the common mode voltage your device level models expect against the common mode voltages your behavioral model produces. You may also want to make sure the input to your clock signal indeed crosses the threshold your behavioral model expects.

Title: Re: clocked comparator in verilog A
Post by Geoffrey_Coram on May 15^th, 2007, 4:03am

My first guess is that the "voltage" discipline is causing trouble when connecting to a real circuit; you should try "electrical" instead for all the ports.

The other thing that struck me as odd was this:

V(vp) <+ hold;
V(vn) <+ -hold;

I'd have expected V(vp, vn) <+ hold; to set up a voltage difference across the pins. What you've got there defines a pair of voltages, one which sets the voltage from vp to ground and the other sets the voltage from vn to ground. This may be releated to Eugene's comment about common-mode voltages.

Title: Re: clocked comparator in verilog A
Post by senyou78 on May 16^th, 2007, 1:43am

thanks for your reply:)

Title: Re: clocked comparator in verilog A
Post by Sarah Ali El-Sayed on Aug 30^th, 2015, 7:06am

I think the model is not working because of the ideal rise and fall properties!
I need help to model a rising edge function?

Title: Re: clocked comparator in verilog A
Post by Ken Kundert on Aug 31^st, 2015, 8:13am

Replace the analog block with:

Code:

analog begin
@(cross((V(Clk)-vth), +1))
hold = V(in) > vth;
out = transition(hold, 0, tt);
V(vp) <+ out;
V(vn) <+ -out;
end

where tt is a nonzero transition time and out is a real variable.

-Ken