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Design >> Mixed-Signal Design >> what is Static phase error in cppfd
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Message started by manisms on May 29^th, 2007, 10:06pm

Title: what is Static phase error in cppfd
Post by manisms on May 29^th, 2007, 10:06pm

what is the static phase error in chargepump and pfd and how this should be measured in spectre
any docs pdf please provide
regard

Title: Re: what is Static phase error in cppf
Post by adesign on May 30^th, 2007, 9:17pm

Static phase offset is the time difference between the averaged input reference clock and the averaged feedback input signal when the PLL is in locked mode. The word average implies that a comparison is made between the input of the PLL and its feedback over several thousand periods, and the resulting time differences are averaged. This method excludes jitter components, hence the name static phase offset.

Title: Re: what is Static phase error in cppfd
Post by manisms on May 31^st, 2007, 8:02am

thanz Adesign
but will this error includes the dead zone also ???
coz the dead zone is also the cp will active even though there is the phase diff between ref clk and fb clk
please clarify

Title: Re: what is Static phase error in cppfd
Post by manisms on May 31^st, 2007, 8:04am

sorry active = not active

Title: Re: what is Static phase error in cppfd
Post by adesign on May 31^st, 2007, 8:50pm

Dead-zone contributes to jitter and hence it is not the part of static-pase offset.

Could you please rephrase the line ---
Quote:

"coz the dead zone is also the cp will active even though there is the phase diff between ref clk and fb clk
please clarify"

Title: Re: what is Static phase error in cppf
Post by joel on Jun 2^nd, 2007, 11:22am

If you don't mind me continuing the discussion, I'm trying to build up my intuition for this stuff...

Can I think of static phase error as the equivalent of skew in a clock tree? Two signals, refclk & synthclk in this case, with a constant offset?

Will a pll have a relatively constant static phase error over a frequency range, or is it really a fixed time interval? If the latter, I'd expect the static phase error of the pll to increase with frequency, as the clock period gets smaller relative to the offset. Am I thinking about this right?

How does deadband behave? I'm imagining the instantanious phase error would slowly increase until it bumps into the end of the deadband, where the PLL will give it a nudge and it will start drifting to the opposite side of the deadband, rattling back and forth so to speak. What sort of patterns might I see when measuring period or phase-error vs. time?

I hope these questions are clear enough to be worth answering. This is confusing stuff for me. Thanks!

Title: Re: what is Static phase error in cppf
Post by adesign on Jun 4^th, 2007, 9:52pm

Quote:

Can I think of static phase error as the equivalent of skew in a clock tree? Two signals, refclk & synthclk in this case, with a constant offset?

Yes

Quote:

Will a pll have a relatively constant static phase error over a frequency range, or is it really a fixed time interval? If the latter, I'd expect the static phase error of the pll to increase with frequency, as the clock period gets smaller relative to the offset. Am I thinking about this right?

I also expect the static phase error to increase with refclk frequency.

Quote:

How does deadband behave? I'm imagining the instantanious phase error would slowly increase until it bumps into the end of the deadband, where the PLL will give it a nudge and it will start drifting to the opposite side of the deadband, rattling back and forth so to speak. What sort of patterns might I see when measuring period or phase-error vs. time?

Whenever the PLL is in deadband, the phase error may increase/decrease depending upon the loop dynamics and the noise in the loop e.g. Power supply noise. However, the correction will only happen when the PLL gets out of this band. You may see a distributed pattern of phase error in deadband.