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Other CAD Tools >> Entry Tools >> Accessing signal values during simulation
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Message started by rajdeep on Jun 22^nd, 2007, 1:26am

Title: Accessing signal values during simulation
Post by rajdeep on Jun 22^nd, 2007, 1:26am

Hi all,

Is it possible to access voltage of a node, or current through a branch during simulation of a circuit using SpectreVerilog. I have heard about ocean interface, which allows post processing of simulated data. But is it possible to do the processing during the simulation.

Rajdeep

Title: Re: Accessing signal values during simulation
Post by Unique on Jul 4^th, 2007, 6:12am

The only thing i could tell You, is that such a feature is now being realized in frames of CAD system AVOCAD, where You could see simulation resilts while You simulating (simulator AVOSpice+ postprocessor AVOProbe). Also i know, that thos program package is relatively cheap.

Good luck!
Dina

Title: Re: Accessing signal values during simulation
Post by haikom on Aug 16^th, 2007, 4:39am

Hi,

what do you mean with accessing signals? It is possible to write a VerilogAMS model to monitor a current and e.g. write a error message to a log file.

Regards, haiko

Title: Re: Accessing signal values during simulation
Post by sheldon on Aug 17^th, 2007, 10:36pm

Radjeep,

Since you said that you wanted to process signals, here are
several ways to process signals while the simulation is running.

1) Add an element to the circuit to process the signal, for
example, using a vcvs to create a differential signal from
two single-ended signals

for ADE users
2) Just use the ADE marching waveforms and do the processing
in the waveform calculator. For example, when simulating
a PLL, use the "freq" function to track whether the PLL locks
or not.

for Spectre RF-Simulink users
3) Use co-simulation and do the processing in Simulink

Best Regards,

Sheldon

Title: Re: Accessing signal values during simulation
Post by sheldon on Aug 18^th, 2007, 4:16pm

Radjeep,

One clarification, Spectre RF - Simulink co-simulation only supports
transient and envelope following analysis.

Best Regards,

Sheldon