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Design Languages >> Verilog-AMS >> initial_step for dc sweep
https://designers-guide.org/forum/YaBB.pl?num=1188397763

Message started by dilbert on Aug 29^th, 2007, 7:29am

Title: initial_step for dc sweep
Post by dilbert on Aug 29^th, 2007, 7:29am

Somehow the "initial_step" block doesn't work for dc sweeps (i'm using cadence 5.10.41).
The block is executed and the values are set correctly, but in the following steps of the sweep all variables are set to zero. (See the example below)

What can I do?

Thanks!

Code:

module veriloga_sweep_test(vout);
output vout;
electrical vout;

real v;
analog begin

@(initial_step) begin
v = 1.0;
end

V(vout) <+ v;
end
endmodule

Title: Re: initial_step for dc sweep
Post by Geoffrey_Coram on Aug 31^st, 2007, 8:13am

You should probably upgrade your version of Spectre.

Back at the time that 5.10.41 was released, there was still some confusion in the Verilog-AMS LRM as to what "initial_step" should do for a dc sweep, since "initial_step" was originally intended for transient analyses.

LRM2.2 specifies when initial_step should be true for various points of various spice-like analyses.

Title: Re: initial_step for dc sweep
Post by tdlrali on Jul 2^nd, 2014, 4:38am

Sorry for unburying this old thread, but I have this exact issue.

I'm trying to simulate the static behavior of a DAC with a DC analysis, using an ideal ADC to provide the digital input for the DAC. I'm using the following VerilogA ADC (from the Verilog-A examples on this site):

Code:

module adc(out, in, clk);
// parameter integer bits = 8 from [1:24];
`define bits 8 // resolution (bits)
parameter real fullscale = 1.0; // input range is from 0 to fullscale (V)
parameter real td = 0; // delay from clock edge to output (s)
parameter real tt = 0; // transition time of output (s)
parameter real vdd = 5.0; // voltage level of logic 1 (V)
parameter real thresh = vdd/2; // logic threshold level (V)
parameter integer dir = +1 from [-1:1] exclude 0;
// 1 for rising edges, -1 for falling
input in, clk;
output [0:`bits-1] out;
voltage in, clk;
voltage [0:`bits-1] out;
real sample, midpoint;
integer result[0:`bits-1];
integer i;

analog begin
@(cross(V(clk)-thresh, dir) or initial_step) begin
sample = V(in);
midpoint = fullscale/2.0;
for (i = `bits - 1; i >= 0; i = i - 1) begin
if (sample > midpoint) begin
result[i] = vdd;
sample = sample - midpoint;
end else begin
result[i] = 0.0;
end
sample = 2.0*sample;
end
end
generate i (`bits-1,0) begin
V(out[i]) <+ transition(result[i], td, tt);
end
end
endmodule
`undef bits

In an DC analysis, the output of the ADC is all low, no matter what the input voltage is. By adding a $debug output, I can see that the analog section/initial_step is only run once (with in=0V), but not for each subsequent DC operating point.

I'm using Cadence/Spectre to simulate. How can I force Spectre to run the analog section / trigger the initial_step for each step?

Spectre Version:
12.1.1.164.isr15

Title: Re: initial_step for dc sweep
Post by Geoffrey_Coram on Jul 8^th, 2014, 7:46am

Have you tried using the "above" event? The description says it is supposed to trigger in dc, unlike cross.