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Design >> High-Speed I/O Design >> current steering logic(CSL) buffer
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Message started by dandelion on Sep 3^rd, 2007, 11:54pm

Title: current steering logic(CSL) buffer
Post by dandelion on Sep 3^rd, 2007, 11:54pm

Hi,
In the mixed signal design, to reduce the di/dt noise, CSL(current steering logic)attract more and more attention.

I am not familar with the CSL and I want to know is there any mature product of mixed mode IC used this technique which ahve replaced conventional static inverter?

Thanks

Title: Re: current steering logic(CSL) buffer
Post by Visjnoe on Sep 4^th, 2007, 10:53am

Dear,

read any decent paper on SerDes RX/TX (PCI Express, SONET, XAUI...) and you will find lots of implementation examples.

Regards

Peter

Title: Re: current steering logic(CSL) buffer
Post by dandelion on Sep 4^th, 2007, 6:39pm

Visjnoe wrote on Sep 4^th, 2007, 10:53am:

Dear,

read any decent paper on SerDes RX/TX (PCI Express, SONET, XAUI...) and you will find lots of implementation examples.

Regards

Peter

Hi,Peter,
Thanks for the reply.

I guess you mean the CML logic( current mode logic). Here, my question is I need the CSL logic buffer to replace the oringinal static inverter buffer(CMOS level). So, the requirement is critical for the low power, high driver capability. I found the Vol and Voh spec of my CSL logic implementing cmos level is not good as static inverter, especially it would be worse when the load sink or source some current. Although its di/dt noise is indeed excellent, I wonder if any product use this technique to implement a CMOS level.

Thanks
Dandelion

Title: Re: current steering logic(CSL) buffer
Post by email_gz on Nov 11^th, 2007, 9:50pm

Hello all:
I think current steering logic(CSL) buffer is just CML. Except CML Driver, maybe Voltage Mode Driver can be used for lower power, but this type of driver is hard design becasue of Z match,and often have small output swing. AMD HT3 IO-link use Voltage Mode Driver with current mode Channel-Pre-Eq.

Title: Re: current steering logic(CSL) buffer
Post by fonseca.ha on Feb 2^nd, 2008, 10:27am

Hello All,
Does anyone has a reference about CSL. I didn't found what is the when compared to CML.
Cheers,
Humberto

Title: Re: current steering logic(CSL) buffer
Post by loose-electron on Feb 26^th, 2008, 6:45pm

Last I checked -

CSL is the same as differential CML

If you research ECL (Emitter coupled logic) designs you will find info on ground referenced CML.
(Look around for data on MECL 10,000 - Motorola's old ECL stuff)

That is an old bipolar version of singled ended CML.

THere exist level shift and convert circuits between CSL and vanilla CMOS logic, amplification to recreate a rail to rail logivc level, in essence.