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Design >> High-Speed I/O Design >> LVDS TX. Design
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Message started by justdoit on Sep 5th, 2007, 9:42pm

Title: LVDS TX. Design
Post by justdoit on Sep 5th, 2007, 9:42pm

Hi all ,
I have a question on LVDS transmitter design . I am using a common mode feedback circuit to stabilize the output common mode voltage and I want to do the stability analysis for this feedback loop.For that I need to get the pole at the output of the LVDS driver .Can anyone suggest what all the resistances and capacitances that come into play while calculating this pole !!!!!  

Title: Re: LVDS TX. Design
Post by neoflash on Sep 9th, 2007, 6:30am

Hi, I think u should be concerned with PCB trace parasitic capacitance. It is not safe to put ur dominant pole at output since the total capacitance will not be controllable and might be too low to keep circuit stable.

I suggest you put dominant pole at your CMFB circuit.

Title: Re: LVDS TX. Design
Post by justdoit on Sep 9th, 2007, 10:26pm

Hi ,
I agree with u that CMFB pole should be the dominant one ...but i want to know at what frequency my output pole comes so that i can adjust the CMFB pole for the required phase margin .For that i need to know some rough estimation of  R and C of the output pole .Please suggest some simple way to model the transmisson line and the terminating resistor (100 ohm), so that i can get the R and C of the output pole from it .....

Title: Re: LVDS TX. Design
Post by email_gz on Nov 28th, 2007, 12:43am

Maybe, The CMFB path BW is less than 1/10 of LVDS AMP Signal path BW .You  can also use hspice wxxx   element with rlgc to simulation the PCB transline ,with ESD Cap(1-2 pF)?

Title: Re: LVDS TX. Design
Post by SATurn on Apr 1st, 2008, 1:29pm

Hello,

Remember that to analyze the CM loop, you should only include the CM impedance ! It means any floating impedance between the two output nodes will be discarded in CM point of view and you just need to put the impedances connected from each output to ground or VDD.

SATurn

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