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Design Languages >> Verilog-AMS >> Verilog-A CP PLL model free from hidden state
https://designers-guide.org/forum/YaBB.pl?num=1189658426

Message started by Aigneryu on Sep 12^th, 2007, 9:40pm

Title: Verilog-A CP PLL model free from hidden state
Post by Aigneryu on Sep 12^th, 2007, 9:40pm

Hi,

I made a chargepump PLL model which can be used in PSS simulation. After I tested VCO and the PFD-CP with spectre, they all works fine, and the VCO can also introduce phase noise. However, when I simulate them in closed-loop configuration, the result of PSS is correct, and the spur level is correct, but the overall phase noise looks like a open-loop one. Can anybody test this for me?

This is the netlist for the PLL test bench

I0 (net013 0) isource dc=0 type=dc noisevec=[ 1k 0 100M 0 ]
V0 (R 0) vsource type=pulse val0=-1 val1=1 period=100n rise=100p fall=100p
I40 (net16 net014 net015 R V) pfd_cp icpp=1m icpn=1.2m vh=1 vl=-1 dir=1 \
tt=1p td=5n ttol=1p init_state=0
I39 (V vctrl) vco_phase amplitude=1 Fc=1000M Fr=100M ratio=100 Fos=1M \
phasenoise=-400
C2 (net7 0) capacitor c=112n
C1 (net18 0) capacitor c=1.4n
C3 (vctrl 0) capacitor c=4.7n
R2 (net18 net7) resistor r=170 isnoisy=no
R3 (net18 vctrl) resistor r=340 isnoisy=no
IPRB0 (net16 net18) iprobe

Title: Re: Verilog-A CP PLL model free from hidden state
Post by Aigneryu on Sep 12^th, 2007, 9:41pm

This is the VCO model

// VerilogA for PLL_noiseSim_toolLib, vco_phase, veriloga

`include "constants.h"
`include "discipline.h"

module vco_phase(vout, in);
input in; voltage in;
//output phiout; phase phiout;
output vout; voltage vout;
voltage vn;
voltage vtune;

parameter amplitude = 1 from [0:inf); // oscillation amplitude
parameter real Fc = 100M from (0:inf); // center frequency
parameter real Fr = 100M from (0:inf); // transfer gain, Kvco (Hz/V)
parameter real ratio = 1 from (0:inf); // division ratio of divider
parameter real Fos = 1M;// from (0:inf); // offset frequency at which phase noise is given
parameter real phasenoise = -120 from [-400:inf); // phase noise level in dBc/Hz
parameter real wn1 = 2*pow(Fos,2)*pow(10,(phasenoise/10)) from [0:inf); // equivalent frequency noise power
parameter real wn2 = 0 from [0:inf); // white output phase noise at 1 Hz (rad2/Hz)
//parameter real fc = 0 from [0:inf); // flicker noise corner frequency (Hz)

real phase;
real frequency;

analog begin
@(initial_step)
begin
phase=0;
frequency=Fc;
end

frequency=(Fc+Fr*V(vtune))/ratio;

V(vtune)<+V(in)+V(vn)/Fr;
V(vn)<+white_noise(wn1, "wpn");

phase= 2*`M_PI*idtmod(frequency, 0, 1, -0.5);
V(vout) <+ amplitude*sin(phase);
V(vout) <+ white_noise(wn2, "wpn");

end
endmodule

Title: Re: Verilog-A CP PLL model free from hidden state
Post by Aigneryu on Sep 12^th, 2007, 9:45pm

This is the chargepump model with finite reset delay (derived from the Ken's Hidden-state-free DFF)

`include "disciplines.vams"
`include "constants.vams"

//
// This model exhibits no jitter
//

module pfd_cp (Icp, up, dn, ref, vco);

output Icp; electrical Icp; // current output
output up; electrical up; // current output
output dn; electrical dn; // current output
electrical rst;

input ref; voltage ref; // positive input (edge triggered)
input vco; voltage vco; // inverting input (edge triggered)

parameter real icpp=100u; // maximum sourcing current
parameter real icpn=100u; // maximum sinking current
parameter real vh=+1; // input voltage in high state
parameter real vl=-1; // input voltage in low state
parameter real vth=(vh+vl)/2; // threshold voltage at input
parameter integer dir=1 from [-1:1] exclude 0;
// dir=1 for positive edge trigger
// dir=-1 for negative edge trigger
parameter real tt=20p from (0:inf); // transition time of output signal
parameter real td=1f from (0:inf); // average delay from input to output
parameter real ttol=1f from (0:inf); // time tolerance
parameter integer init_state=0 from [0:1];

integer actNow, out_ref, out_vco, state_ref, state_vco, state_rst;

analog begin
// @(cross((V(ref)-vth), dir, ttol))
// if (state > -1) state = state - 1;
// @(cross((V(vco)-vth), dir, ttol))
// if (state < 1) state = state + 1;

actNow = 0;

@(initial_step) begin
actNow = 1;
state_ref = init_state;
state_vco = init_state;
end

@(cross(V(ref) - vth, dir) or cross(V(rst) - 0.5, +1)) begin
actNow = 1;
state_ref = (V(rst) < 0.5);
end

@(cross(V(vco) - vth, dir) or cross(V(rst) - 0.5, +1)) begin
actNow = 1;
state_vco = (V(rst) < 0.5);
end

out_ref = idt(0, state_ref, actNow);
out_vco = idt(0, state_vco, actNow);
V(up) <+ transition(out_ref ? vh : vl, td, tt);
V(dn) <+ transition(out_vco ? vh : vl, td, tt);

I(Icp)<+ transition(out_ref ? -icpp : 0, td, tt);
I(Icp)<+ transition(out_vco ? icpn : 0, td, tt);

end
endmodule

Title: Re: Verilog-A CP PLL model free from hidden state
Post by Aigneryu on Sep 12^th, 2007, 9:47pm

Basically, when I check the phase noise from pnoise analysis, the output phase noise
from the locked VCO will still look exactly the same as the result from un-locked (free running)
VCO.

Sincerely,

Title: Re: Verilog-A CP PLL model free from hidden state
Post by Frank Wiedmann on Sep 12^th, 2007, 11:41pm

Your problem seems to be similar to the one described in http://www.designers-guide.org/Forum/YaBB.pl?num=1107716368/49#49.

Title: Re: Verilog-A CP PLL model free from hidden state
Post by Ken Kundert on Sep 13^th, 2007, 1:21am

The abrupt switching nature of the pfd-cp is blocking the small signal noise propagation. To pass small signal, the model has to be smooth.

This is an important point, just because models have no hidden state, and so converge in pss, does not mean they work as desired in the small-signal analyses. They must also be smooth.

-Ken

Title: Re: Verilog-A CP PLL model free from hidden state
Post by Aigneryu on Sep 13^th, 2007, 7:50am

Thanks all,

Yes, I found this effect from the threshold detecting nature of the FF. If I changed the PFD to real transistors, the small signal can pass it.

Sincerely,

Title: Re: Verilog-A CP PLL model free from hidden state
Post by ellarguero on Apr 12^th, 2012, 8:02pm

Ken Kundert wrote on Sep 13^th, 2007, 1:21am:

Hi Ken,

Is it possible to give some highlights upon the relation between small signal blocking and smoothness of the model
and what do you mean by smooth, ? the transition filter gives smoothness through rise and fall times, is it this what you mean by smoothing? there is however a 1st derivative discontinuity anyway.

so just to summarize, what's smoothness requirement for pac simulation following a pss

thanks a lot

Title: Re: Verilog-A CP PLL model free from hidden state
Post by Forum Administrator on Apr 13^th, 2012, 1:01am

The requirement is not that the output signal be a continuous function of time. Rather what I mean is that the input to output transfer function must a continuous function of the input signal. This is required so that there is an interval, however brief, that the small signal at the input is able to pass though the noise component to the output. For example, if you model an inverter with:

Code:

V(out) <+ Vdd*(V(in) < thresh);

then there is no value of the input signal for which the output varies in proportion to the input. Even

Code:

@(cross(V(in) - thresh)
;
V(out) <+ Vdd*transition(V(in) < thresh), 0, 1n);

does not work for the same reason, even though the output signal is a continuous function of time. The problem is that the output is a discrete function of the input.

Instead you should model the input/output relationship with something smooth, like a tanh() function. You also need to assure that the simulator places at least one time point in this region. So you should consider a model something like

Code:

@(cross(V(in) -thresh)
;
V(out) <+ Vdd*(tanh(a*(V(in)-thresh)) + 1)/2;

or something similar (don't take this model too seriously, it is just the first thing that came into my head, and it is suitable for something like an inverter, not a PFD). The tanh() function is continuous from input to output, and the cross function assures that the simulator places at least one point in the 'linear' region.

-Ken

Title: Re: Verilog-A CP PLL model free from hidden state
Post by ChristianAMS on Sep 5^th, 2016, 1:38am

Dear All,
at first I want to thank you guys for the work you do here. It helped me a lot during the last time.
I'm currently designing a PLL in cadence. I wanted to seperate the PFD from the charge pump noise. That's why I was looking for a PFD model that runs with pss/pnoise analysis.
For the PFD/CP model below I get an error saying, that the variables state_vco and state_ref are hidden states. Read the DFF post and the hidden state paper, I wasn't able fix it up to now. Could you give me a hint how to get rid of the two hidden states?

I'm using
MMSIM 10.11.200

Regards,
ChristianAMS