The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Measurements >> Phase Noise and Jitter Measurements >> 6ps rms jitter spec
https://designers-guide.org/forum/YaBB.pl?num=1190100020

Message started by satya on Sep 18th, 2007, 12:20am

Title: 6ps rms jitter spec
Post by satya on Sep 18th, 2007, 12:20am

Hi,

I come across a spec of 6ps rms jitter for a pll.
what actually this refers to? and feasible?
is this random jitter?
generally the jitter  what we calculate from phase noise is what jitter type?
please give ur comments

Title: Re: 6ps rms jitter spec
Post by Stefan on Sep 21st, 2007, 11:30am

This could be all type of jitter, you should be a bit more specific or cite the source of it.
You should also check Ken's Work on jitter and phase noise to gain some more insight about the possible types (you could also check the papers of A.Demir, Hajimir or Drucker).

Title: Re: 6ps rms jitter spec
Post by buckaroo on Oct 23rd, 2007, 9:32pm

according to your output frequency, it is feasible. the lower the output frequency, the less feasible



satya wrote on Sep 18th, 2007, 12:20am:
Hi,

I come across a spec of 6ps rms jitter for a pll.
what actually this refers to? and feasible?
is this random jitter?
generally the jitter  what we calculate from phase noise is what jitter type?
please give ur comments


Title: Re: 6ps rms jitter spec
Post by imtired on Nov 15th, 2007, 10:53am

Depending on what the PLL includes, the 6ps rms jitter could be referring to the PFD/CP residual noise, or if it has a VCO then it may include that as well.

To determine feasibility, you really need to look at the phase noise characteristics of the PLL in order to make an accurate assessment.  Some things that can degrade jitter are:
- a noisy reference oscillator
- a noisy output oscillator
- a high multiplication factor coupled with noisy PFD/CP/divider/ref osc.
- loop BW also can affect noise

There are many different kinds of reference oscillators, PLL chips, and VCOs out there, at many different frequencies.  Depending on your frequncy, I'm pretty sure you'll be able to find something commercial off the shelf components to meet the performance criteria of 6ps rms.  You might also have to consider spurs too, which I don't think an rms spec would capture that information.

Regarding jitter - I've always thought that rms jitter refers to random jitter, and that deterministic jitter is captured in a peak-to-peak spec.  In phase noise terms, the rms jitter is found by integrating the noise spectral density, whereas deterministic jitter is found from the spurs.  Is that true/false?

Title: Re: 6ps rms jitter spec
Post by smlogan on Nov 16th, 2007, 8:35am


satya wrote on Sep 18th, 2007, 12:20am:
Hi,

I come across a spec of 6ps rms jitter for a pll.
what actually this refers to? and feasible?
is this random jitter?
generally the jitter  what we calculate from phase noise is what jitter type?
please give ur comments


I would recommend you explore the genesis of the requirement. I believe you need a bit more information to properly break the requirement down to requirements for the individual components of your phase-locked loop. Typically, a standard drives the jitter generation requirement for a phase-locked loop. Most all standards (expect SONET/SDH) break the jitter down ino a requirement for both random and deterministic jitter components.  Specific questions that I would try to resolve are:

1. The bandwidth over which the 6 ps rms jitter requirement is measured
2. The manner in which the 6 ps rms jitter is to be measured (this provides insight into the type of jitter to which the requirement is referring)
3. If a data recovery based phase-locked loop (i.e., a CDR), the data pattern applied to the input during which the jitter is measured
4. If a data recovery based phase-locked loop (or if the clock is used to retime data) , the bit error rate over which the jitter requirement exists

As for a 6 ps jitter being feasible, many phase locked loops are capable of providing a 6 ps rms random output jitter component  for jitter measurement bandwidths of 10 kHz and greater. The issue of course, is highly dependent on the jitter of the reference clock to the PLL, the bandwidth and jitter transfer of the PLL and the internal VCO noise of the PLL. Hence, there is not a "general" answer.

Finally, phase noise data contains both random and determistic jitter. One must take efforts to examine the random and deterministic components when computing the jitter through the use of bandwidth limiting, applying specific data patterns and jitter decomposition.

Hope this helps,

Shawn

The Designer's Guide Community Forum » Powered by YaBB 2.2.2!
YaBB © 2000-2008. All Rights Reserved.