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Design Languages >> Verilog-AMS >> syntax error for string parameter
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Message started by lily on Oct 3^rd, 2007, 7:35pm

Title: syntax error for string parameter
Post by lily on Oct 3^rd, 2007, 7:35pm

I am trying to use string type parameter in my veriloga model like below, the spectre simulator always complain syntax error. I have checked the spectre veriloga reference, it gives the example same as mine. Is there anyone know why I cannot use this string parameter?

Thanks!

--------------------------------------------------------
module INV( in,out,vdd,gnd );
input in,vdd,gnd;
output out;
electrical in,out,vdd,gnd;

parameter real Cin_in1=9.342169858000004E-12 ;
parameter real Cout=1.7384E-14*2 ;
parameter string proc="typ";
......................................
-----------------------------------------------------------

Error found by spectre during AHDL read-in.
"./INV.va", line 15: "parameter string <<--? proc ="typ";"
"./INV.va", line 15: Error: syntax error

Title: Re: syntax error for string parameter
Post by Geoffrey_Coram on Oct 8^th, 2007, 4:54am

What version of Spectre are you running?

In some cases, you may be able to simply omit "string" -- I think this makes the parameter an integer type, where the bytes are set by the ascii values of the string literal ("typ"), so you can do some comparisons on it in the module.

Title: Re: syntax error for string parameter
Post by lily on Oct 11^th, 2007, 6:41pm

Thanks for reply. Actually cadence 6.0 supports the string parameter and it seems lower version does not.

//lili