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https://designers-guide.org/forum/YaBB.pl Design >> RF Design >> Digital Sigma Delta for Fractional PLL https://designers-guide.org/forum/YaBB.pl?num=1195012264 Message started by tm123 on Nov 13th, 2007, 7:51pm |
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Title: Digital Sigma Delta for Fractional PLL Post by tm123 on Nov 13th, 2007, 7:51pm Hello, I am trying to design a sigma delta modulator for a fractional PLL. I plan on using a 3rd order modulator, with multi-bit quantizer. The architecture I would like to use is 'multiple feed forward', which seems to be common in fractional pll's. The one thing I am not sure of is how to calculate the stable input range of the modulator. Is it dependent on the number of bits in the quantizer, or the NTF, or both? Is there good literature I can use to learn about this? Thanks in advance. Tim |
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Title: Re: Digital Sigma Delta for Fractional PLL Post by pancho_hideboo on Nov 13th, 2007, 11:55pm Quote:
If your multi-bit quantizer is more than 4bits, a stability is almost determined by NTF. Quote:
Following is a good book as introduction. http://www.designers-guide.org/Books/#Schreier-2004 |
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Title: Re: Digital Sigma Delta for Fractional PLL Post by tm123 on Nov 14th, 2007, 7:46am Thank you for your comments. I have the book 'Understanding Delta Sigma Data Converters' so I will take a look in there. I think the quantizer is going to be 7 bits. So can the stable input range be determined from plotting the poles/zeros of the NTF in the z plane? Thanks again. Tim |
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Title: Re: Digital Sigma Delta for Fractional PLL Post by tm123 on Nov 16th, 2007, 8:43am Sorry, I mistakenly said the quantizer would be 7 bits. It will be 3 bits for 7 levels. Tim |
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