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Design >> High-Speed I/O Design >> XAUI/CEI standard PLL 3dB bandwidth
https://designers-guide.org/forum/YaBB.pl?num=1195567866

Message started by neoflash on Nov 20^th, 2007, 6:11am

Title: XAUI/CEI standard PLL 3dB bandwidth
Post by neoflash on Nov 20^th, 2007, 6:11am

For serial link, a lot of specifications specify PLL bandwidth, such as PCIE.

However, for xaui and cei, there is no such spec. Does it means people can do anything they want?

Title: Re: XAUI/CEI standard PLL 3dB bandwidth
Post by ywguo on Jan 14^th, 2008, 1:30am

Hi neoflash,

Is that the PLL for transmitter or receiver?

I remember that the jitter tolorence is defined in the XAUI spec, from which the PLL bandwidth can be derived. Please refer the IEEE 802 standard for the physical layer of XAUI.

Yawei

Title: Re: XAUI/CEI standard PLL 3dB bandwidth
Post by neoflash on Jan 14^th, 2008, 2:28am

ywguo wrote on Jan 14^th, 2008, 1:30am:

Yes, rx bandwidth can be infered. What about TX?

Title: Re: XAUI/CEI standard PLL 3dB bandwidth
Post by ywguo on Jan 17^th, 2008, 12:38am

Hi neoflash,

The jitter tolerance is implicitly or explicitly defined the standard. Sure the jitter generation should be smaller than the jitter tolerance to ensure the proper data transmission. So it defined the TX PLL bandwidth implicitly.

Another method is to reduce the total jitter to meet the eye-diagram mask. However, I am not clear the relation between the bandwidth and the total jitter. That is quite complex. Perhaps the random jitter (rms jitter) can be deduced from the integral phase noise, which strongly depends on the TX PLL bandwidth. However, periodic jitter, ISI, and duty cycle distortion add to the total jitter. Those factors are independent of TX PLL bandwidth.

I hope the reply is helpful.

Yawei