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Design >> High-Speed I/O Design >> ssn minimization in LVDS transmitter
https://designers-guide.org/forum/YaBB.pl?num=1196745494

Message started by justdoit on Dec 3^rd, 2007, 9:18pm

Title: ssn minimization in LVDS transmitter
Post by justdoit on Dec 3^rd, 2007, 9:18pm

Hi all,
I am designing a LVDS transmitter .I want to minimize peak current flowing through DVDD supply(to minimize the SSN noise ) .In order to achieve this wat is the criteria for the signals that drive the transmitter switches w.r.t to thier timing issues

Title: Re: ssn minimization in LVDS transmitter
Post by email_gz on Dec 8^th, 2007, 4:17am

careful design symmetry (delay path,cap loding...)of differential siganls which drive the LVDS switchs, and also slew rate should not too fast. I think :)

Title: Re: ssn minimization in LVDS transmitter
Post by fonseca.ha on Feb 2^nd, 2008, 10:19am

A comment about speed of the edges when driving the steering devices of the LVDS driver. A possible problem is that you may end up with too much jitter in the TX.

is DVDD your digital supply?