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Design >> Analog Design >> Accumulation mode capacitor
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Message started by Berti on Jan 11^th, 2008, 8:23am

Title: Accumulation mode capacitor
Post by Berti on Jan 11^th, 2008, 8:23am

Hi all,

I like to use a MOS transistor in accumulation-mode for decoupling of bias voltages.
On the left-side of the attached figure, an accumulation-mode varactor is shown as provided by the design-kit
I am using.
My question is the following:
Can I also use a MOS transistor as drawn on the right-side of the figure. Are there any
problems? And what is the difference between the two structures (ESR etc.)?

Thank you, Regards

Title: Re: Accumulation mode capacitor
Post by fran2k5 on Jan 12^th, 2008, 7:33am

Hi Berti,

the only difference between the two structures is their C-V characteristics.
While the PMOS-based one has an inversion region for which C=Cox, the other structure (on the left) does not have it.
As far as the gate on the PMOS is higher than its source/drain voltage the accumulation cap is going to work.

Regards,

fran2k5

Title: Re: Accumulation mode capacitor
Post by Berti on Jan 12^th, 2008, 8:11am

Thank you Frank. You confirm what I have expected.