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Modeling >> Semiconductor Devices >> Analog transistors in deep-nwell
https://designers-guide.org/forum/YaBB.pl?num=1202371854

Message started by Berti on Feb 7^th, 2008, 12:10am

Title: Analog transistors in deep-nwell
Post by Berti on Feb 7^th, 2008, 12:10am

Hi all,

The technology I use offers deep (or buried) nwells. I am wondering whether the deep nwell will change the characteristics of the devices?
Because I assume that the transistor models haven't been measured for devices isolated by a deep-nwell(?) What difference can I expect
for transistors isolated by a deep nwell ... or can I neglect the influence.?.

Thanks for inputs!

Title: Re: Analog transistors in deep-nwell
Post by Geoffrey_Coram on Feb 7^th, 2008, 6:30am

I don't know if there's any significant difference between a device in a (pwell in a) deep nwell versus one just in the p substrate.

However, I do know that there's a lot of work on the "well proximity effect", where the transistor is significantly altered if the *edge* of an nwell is close to it. This is because the high-energy implant scatters off the blocking material (photoresist) and into the active area of the device. You should be able to find more info by searching for WPE.

(Presumably, the high-energy implant passes through the active region of the device that's not near the edge, so the device won't be altered much.)

Title: Re: Analog transistors in deep-nwell
Post by Berti on Feb 7^th, 2008, 10:32pm

Thank you Geoffrey for the input!

I also found a publication from Jiong-Guang Su et al. "Improving the RF Performance of 0.18um CMOS With Deep n-Well Implantation" published in IEEE Electronic Device Letters.
The authors provide measurements from a 0.18um technology and basically claim that DC characteristics aren't altered but Cgs can be reduced by up to 20% when using deep nwell.

Regards

Title: Re: Analog transistors in deep-nwell
Post by vivkr on Feb 8^th, 2008, 12:19am

Hi Berti,

If the foundry offers devices in deep nwell, then it should normally also offer you models based on characterisation
of such devices. Depending on the foundry, there may be some/a lot of differences between these devices (isolated)
and standard nonisolated devices in a pwell process. Typically, I would expect that atleast the basic operation is
quite similar.

Which process is it by the way? Perhaps if someone else is using this process, they could tell you whether the models
are obtained from a characterisation of nwell devices or not.

Regards
Vivek

Berti wrote on Feb 7^th, 2008, 12:10am:

Title: Re: Analog transistors in deep-nwell
Post by Berti on Feb 8^th, 2008, 2:21am

I am using 130nm and 65nm processes from ST.

Does anybode have expierence from other processes where special "deep nwell models" are available?

Regards

Title: Re: Analog transistors in deep-nwell
Post by thechopper on Feb 25^th, 2008, 4:54pm

Hi Berti,

I´m currently using a process with special deep nwell models. However - as Vivek pointed out correctly - basic operation is quite similar for the isolated and non-isolated devices. The differences mainly reside on the isolation junctions modeling, these junctions obviously not being present in the case of non-isolated devices. These might play a role when operating the device at high temperature (leakage currents) or might become important in case the device is, for example, connected to input/output interfaces that can be subjected to larger than normal operation voltages.
Finally, parasitics are certainly different and might also play a role in the device AC response, although this might only be important at relatively high frequencies.

Regards
Tosei

Title: Re: Analog transistors in deep-nwell
Post by Berti on Feb 25^th, 2008, 10:20pm

Hi Tosei,

The guys from the paper

Quote:

I also found a publication from Jiong-Guang Su et al. "Improving the RF Performance of 0.18um CMOS With Deep n-Well Implantation" published in IEEE Electronic Device Letters.

claim that transistors in deep n-well have smaller cgs. However, they leave the buried nwell floating. Considering latch-up I am not sure if that is a good idea (also since the design-rules
prohibit that in the technology I am using).

Tosei, can you confirm the smaller parasitics (approx. 20%) when simulating the deep nwell models?

Regards

Title: Re: Analog transistors in deep-nwell
Post by Terence on Jul 22^nd, 2009, 2:24am

Hi all,

I am wondering if nMOS in floating DNW is not good for latch-up immunity.
Can anyone share the knowledge?

Thanks very much!

Title: Re: Analog transistors in deep-nwell
Post by weber8722 on Nov 18^th, 2011, 12:19am

Hi,

Geoffrey_Coram wrote on Feb 7^th, 2008, 6:30am:

I don't know if there's any significant difference between a device in a (pwell in a) deep nwell versus one just in the p substrate.

I think beside isolation for reducing crosstalk there is one major difference!! With DNW you can bootstrap the bulk. This allows much better source followers with gain close to unity. With normal nmos the bulk effect reduces the gain a lot (like down to 0.9 >:( >:(). Also the shift in VTO vs Vbulk is not not and be be highly reduced with DNW :).

Bye Stephan

Title: Re: Analog transistors in deep-nwell
Post by loose-electron on Nov 21^st, 2011, 2:33pm

I helped define the deep n-well structures in the IBM SiGe processes.

They don't help that much with noise coupling.

Whats the issue?

Latch up and isolation? Its all about keeping things properly reverse biased and liberal use of contacts in the biasing.