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Design >> Analog Design >> conditional stability
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Message started by safwatonline on Feb 15th, 2008, 10:02am

Title: conditional stability
Post by safwatonline on Feb 15th, 2008, 10:02am

Hello,
Can any body explain the case conditional stability, i see it like in high order SD-ADC where the gain is larger than one and the total phase of 0 degree yet the system is said to be conditionally stable.
any reference would be great!
 

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