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Design Languages >> VHDL-AMS >> Pipeline 1.5 bit/stage architecture
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Message started by electronique1984 on Mar 4^th, 2008, 3:49am

Title: Pipeline 1.5 bit/stage architecture
Post by electronique1984 on Mar 4^th, 2008, 3:49am

Hi,somebody can help me about a pipeline 1.5 bit/stage architecture model in VHDL-AMS.... :'( :'(

Title: Re: Pipeline 1.5 bit/stage architecture
Post by jbdavid on Jul 2^nd, 2008, 9:41pm

I have one in verilogams I presented in a tutorial at BMAS in 2001 (I think) www.bmas-conf.org
covers the architecture, and how the model should work..
Good luck!

Title: Re: Pipeline 1.5 bit/stage architecture
Post by imd1 on Jul 3^rd, 2008, 3:09am

jbdavid wrote on Jul 2^nd, 2008, 9:41pm:

I have one in verilogams I presented in a tutorial at BMAS in 2001 (I think) www.bmas-conf.org
covers the architecture, and how the model should work..
Good luck!

Would you mind making your modeling files available ?

Title: Re: Pipeline 1.5 bit/stage architecture
Post by jbdavid on Aug 27^th, 2008, 1:29am

you can down load the entire presentation.. on from the ARchive on the BMAS website..
Its not in VHDL so you;ll have to translate anyway.. but that work was done a couple of companies ago.. so I don't think I can get the files anymore..
maybe your cadence AE can ask Ron Vogelsong from them if he still has them..