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Design >> Analog Design >> high loop gain unity-gain buffer, rail-to-rail
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Message started by jiesteve on Mar 27^th, 2008, 10:18am

Title: high loop gain unity-gain buffer, rail-to-rail
Post by jiesteve on Mar 27^th, 2008, 10:18am

Hi,

I'm designing a high speed, unity-gain amplifier. It has a settling time of 15ns, driving a capacitive load of 60pF. I'm using a current mirror OTA architecture, with NMOS inputs. Common mode range is 0.9V to 1.35V with a minimum supply VDD of 1.6V (eek). Nominal gain is 40ish dB, which drops to 30 dB with the 1.35V input and VDD=1.6V (current mirror approaching linear region).

Could somebody suggest an architecture (rail-to-rail?) that does not lose as much gain when the inputs approach the rails?

Thanks!

Title: Re: high loop gain unity-gain buffer, rail-to-rail
Post by SATurn on Apr 1^st, 2008, 1:09pm

Hello,

The simplest topology that I can imagine is single stage folded-cascode amplifier. It has both high input common-mode range and high output swing. On the other side the load capacitance in your case is so high and also you would like to get close to VDD very much. In this case a two stage amplifier can be a better choise. It can provide a higher output swing as well as some kind of decoupling of load capacitance and GBW ...

SATurn

Title: Re: high loop gain unity-gain buffer, rail-to-rail
Post by Pravesh Kumar Saini on Oct 20^th, 2014, 9:40pm

Hi,
Sorry to jump into this thread, actually I want to know the simplest on chip ckt for level shifting 0.5V-0.65V differential signal(BW=500MHz) into 0.4V-1.3V to drive ADC(1V or 2.5V). I got issues with super source follower with output common mode control, so I want to try a closed loop(op-amp) based solution for this.

Title: Re: high loop gain unity-gain buffer, rail-to-rail
Post by loose-electron on Oct 21^st, 2014, 11:27pm

look into the double differential pair input - one diff pair PMOS the other diff pair NMOS for better rail to rail input characteristics.

Look thru IEEE JSSC archives they cover the method there in some older papers

Title: Re: high loop gain unity-gain buffer, rail-to-rail
Post by LazyDesigner on Oct 23^rd, 2014, 9:41pm

loose-electron wrote on Oct 21^st, 2014, 11:27pm:

Sorry, I couldn't understand your opinion. In my case input common mode is 0.5V-0.65V, I need to shift this 500MHz BW signal into 0.4V-1.3V output common mode signal with high linearity(OIP3>18dBm for -7dBm input differential signal). It would be great if you can point to one reference for the same.

Title: Re: high loop gain unity-gain buffer, rail-to-rail
Post by loose-electron on Oct 27^th, 2014, 1:25am

look for rail to rail OTA designs.