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Design Languages >> Verilog-AMS >> Absdelay function implementation
https://designers-guide.org/forum/YaBB.pl?num=1207152782

Message started by lobarth on Apr 2^nd, 2008, 9:13am

Title: Absdelay function implementation
Post by lobarth on Apr 2^nd, 2008, 9:13am

Hi

I discover verilog-a last Thursday. I would like to execute once the absdelay() function. I do not succeed in establishing an "if" condition. Has anyone an idea to solve my life??

Sincerly

LB Faber

Title: Re: Absdelay function implementation
Post by lobarth on Apr 3^rd, 2008, 7:05am

A good night is often enough to understand better model language. ;D

Title: Re: Absdelay function implementation
Post by pancho_hideboo on Apr 3^rd, 2008, 8:18am

lobarth wrote on Apr 3^rd, 2008, 7:05am:

A good night is often enough to understand better model language. ;D

Have you found out work around by yourself ?

Title: Re: Absdelay function implementation
Post by lobarth on Jun 12^th, 2008, 6:59am

Yes, in fact I did not understand correctly the function absdelay. I found after some time that the function "transition" fit my will in a better way.