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Design >> RF Design >> Predicting spurs in PLL frequency synthesizers
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Message started by Gines on Apr 17th, 2008, 1:56am

Title: Predicting spurs in PLL frequency synthesizers
Post by Gines on Apr 17th, 2008, 1:56am

Hi friends,

I am a beginner RF designer and I have implemented a PLL frequency synthesizer at 2.5GHz with a 2.5MHz clock reference and 30kHz loop bandwidth. During testing I have detected a great number of spurs within the whole bandwidth of interest from 30kHz up to 10MHz offset from the carrier. Although references harmonics at multiples of 2.5MHz are no-significant, the spur amplitudes are always about 20dB over the phase noise floor.

The justification of this behaviour is out of my knowledge. In this sense, I wonder,

1.- Could these spurs be caused  by the non-idealities of the charge-pump (output resistance, mismatching,…) or the integer frequency divider (8/9 prescaler, 120-program counter and 5-bit swallow counter)?. If this is the case, is there any simulation method or analytical procedure to predict such behaviour?. I have revised the literature but I have not found any solution.

2.- Could the test setup produce these effects?

Thank you very much in advance.
Gines

Title: Re: Predicting spurs in PLL frequency synthesizers
Post by loose-electron on Apr 17th, 2008, 2:58pm

some more details on your circuit architecture and similar details would be helpful to people trying to answer your questions.

For example - is this a ring oscillator or LC VCO structure?
What are your circuits schematics?
Any and all details like that are informative as a starting point.

Also, you talk of "testing" and then ask about if its in the simulator. Is this lab testing of silicon or looking at the results of simulations?

Please some more details and we shall try our best to help you out.

Jerry



Title: Re: Predicting spurs in PLL frequency synthesizers
Post by Gines on Apr 18th, 2008, 12:40am

Hi,

The PLL has been already fabricated in a 90nm CMOS process. At the moment it is being tested. As mentioned in my post, we have found a great number of spurs in the density power spectrum of the phase noise, and I wonder if it is possible to predict this behaviour by electrical simulations or analytical equations for a next integration? Is there any method to evaluate spurs in frequency synthesizer with several orders of magnitude between the oscillation frequency (2.4GHz) and the close-loop bandwidth (30kHz)? Could a not proper test setup justify this effect?

The RF section of the PLL is constituted by a LC-tank VCO working at 4.8GHz  (sensitivity of 370MHz/V) followed by a SCL divider-by-2 for I/Q generation (Kvco = 2*pi*370/2). Two CMOS inverter buffers the inputs and outputs of the divider-by-2 for isolation purpose. I simulated this section in all process and environment corners following the forum’s recommendations with SpectreRF and this phase noise estimation has a good agreement with the chip test results. When the PLL loop is opened, the response of the VCO and the divider-by-2 exhibits not spurs excepting by a very small component at the reference frequency due to coupling in the test-setup (the swallow frequency divider cannot be disabled).

The band-base section of the PLL is constituted by the classical NAND-based phase/frequency detector with 1ns delay. The charge-pump uses a complementary current-steering topology with boosted cascode transistors to improve the output resistance. It drives 100uA. An external 2nd order passive filter with C1=2nF, R1=7kOhms and C2 = 300pF is implemented at the PCB level.

The chip employs a 1.2V supply with separated pad rings for a good RF isolation. The VCO and the divider-by-2 polarization were independently routed to different pads. It is encapsulated in a 40-pin . PLL high frequency test is performed though an on-chip CMOS inverter buffer.

If you need more information, please let me know and I will provide it.

Thank you again,
Gines.

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