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Other CAD Tools >> Entry Tools >> generating schematics from (cdl/verilog/etc?)
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Message started by analog2000 on May 4^th, 2008, 7:33am

Title: generating schematics from (cdl/verilog/etc?)
Post by analog2000 on May 4^th, 2008, 7:33am

Hi
I have this pdk from tsmc for pad cells. They have only provided cdl netlist, verilog netlist, etc but NO schematics. Would anyone like to share a procedure to generate transistor level schematics that can be simulated in spectre ?
thanks
analog2000

Title: Re: generating schematics from (cdl/verilog/etc?)
Post by ywguo on May 8^th, 2008, 4:54am

Hi,

The below is the an example.

Open icfb, Click Import -> CDL… in CIW. Fill in CDL netlist File: Output Library: Top Cell: Reference Library List: Device-Map File:
The Reference Library contains tsmc18rf and analogLib, where tsmc18rf is the PDK library provided by TSMC. The analogLib is put in the reference library list because a resistor symbol is required while the symbol in tsmc18rf does not generate the dimension and value correctly.
The Device-Map File is titled map.in here and shown below.
devMap := nfet nmos3v
propMatch :=subtype ND
devMap := nfet nmos2v
propMatch := sybType N
devMap := pfet pmos3v
propMatch := subType PD
devMap := pfet pmos2v
propMatch := subType P
devMap := diode dioden3v
propMatch := subType DB
devMap := resistor res
propMatch := subType rp
devMap := resistor rnplus
propMatch := subType rnodrpo_m

Edit the netlist, append the following in each card for resistor.
$[rp] W=1U L=1U M=1
Add the following lines if there are resistor, capacitor, diode, or triode.
PARAM
*.BIPOLAR
*.RESVAL
*.CAPVAL
*.DIOAREA
*.SCALE METER

Comment the line below,
.GLOBAL VSSPST VDD VSS VD33 POC
otherwise pins VSSPST VDD VSS are not generated in the schematic. I don’t know the reason why it does not inhibit VD33 and POC in the generated schematic. BTW, Global Node Expansion is chosen as Full in Virtuoso® CDL In window. What does it mean?

Good luck!
Yawei