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Design Languages >> Verilog-AMS >> Delay in Verilog-A
https://designers-guide.org/forum/YaBB.pl?num=1210828245

Message started by ssdfz on May 14^th, 2008, 10:10pm

Title: Delay in Verilog-A
Post by ssdfz on May 14^th, 2008, 10:10pm

Hi all:

I read Ken's book on Verilog-AMS and it says that delay (using '#’） and wait statements are not allowed. I was just wondering how to achieve a function such as the one below in Verilog-A
if (condition) begin
# time;
statement;
end
I am kind of clueless in dealing with this situation in verilogA.

Thank you in advance for your invaluable opinions!
Erik

Title: Re: Delay in Verilog-A
Post by jbdavid on May 15^th, 2008, 3:47am

1 way use a timer..
at the event where you want to start the delay you set the timer trigger point..
and then in the timer event you take the second actions.

Alternatively if your second action is something like a transition, the function has a builtin delay value..

or you can filter your continuous output thru an $absdelay filter..

Title: Re: Delay in Verilog-A
Post by ssdfz on May 15^th, 2008, 9:42am

The waveform manipulation that i really wished to do is sth like
@(above(a-b)) //when a>b
c = V(VDD);
@(above(b-a)) // when b<a
# 100 (but this is not supported by va)
c= V(VSS);

The current way I am dealing with this situation is to feed c into a transition filter with asymmetric tr and tf, and then they will cross vth at different time. But I thought there might an efficient way dealing this kind of situation. I am not sure if timer is able to handle that -- it seems to me that it generates periodic event. I will look into it. Thanks for your reply!

Title: Re: Delay in Verilog-A
Post by Ken Kundert on May 15^th, 2008, 11:06am

Try something like ...

Code:

@(above(a-b)) //when a>b
c = V(VDD);
@(above(b-a)) // when b<a
next = $abstime+100*`tick
@(timer(next))
c= V(VSS);

where `tick is defined to contain the time units from `timescale (next and $abstime use seconds).

The timer function generates periodic events only if the second argument is given.

-Ken

Title: Re: Delay in Verilog-A
Post by ssdfz on May 15^th, 2008, 2:01pm

Thanks a lot Ken!

It seems that neither hspice nor hsim would accept the syntax "`timescale" (I guess they can just deal with Verilog-A but not Verilog-AMS); I don't know if there is any Synopsys tool will handle Verilog-AMS (only synopsys tools are available to my flow).
So instead of writing "next = $abstime+100*`tick", i wrote something like "next = $abstime+100n".
It functions well but I don't know if they are equivalent in terms of simulator's computation resource.
I am building a Verilog-A model for a system with many blocks, so I am kind of avoiding any expensive command.

Erik

Title: Re: Delay in Verilog-A
Post by ywguo on May 30^th, 2008, 12:40am

Hi,

Quote:

or you can filter your continuous output thru an $absdelay filter..

I tried to delay a voltage input while running a transient simulation. It looks like the following.

Code:

electrical vin;
realy vin_delay;
vin_delay = absdelay(V(vin),10n);

The spectre simulator reported the following warning message.
Warning from spectre during AHDL read-in.
"/export/home/myhome/work_libs/dac_inl_10bit/veriloga/veriloga.va", line 87: Warning: '(abs)delay()" does not account for phase shift in small-signal analysis.

What does that mean?

Thank you in advance.
Yawei

Title: Re: Delay in Verilog-A
Post by Ken Kundert on May 30^th, 2008, 3:51pm

It means that using the small signal analyses (AC, XF, noise, etc) on a circuit that contains absdelay will give the wrong results because absdelay does not have an small-signal implementation.

-Ken

Title: Re: Delay in Verilog-A
Post by ywguo on Jun 1^st, 2008, 4:37am

Thank you, Ken.

Yawei