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Design >> Mixed-Signal Design >> PLL settling time and lock time
https://designers-guide.org/forum/YaBB.pl?num=1213890534

Message started by keikei on Jun 19^th, 2008, 8:48am

Title: PLL settling time and lock time
Post by keikei on Jun 19^th, 2008, 8:48am

what is the difference between them? or two expressions for the same concept?

Title: Re: PLL settling time and lock time
Post by buddypoor on Jun 21^st, 2008, 2:35am

It´s just a matter of definition; R.E. Best (Textbook: Phase-lock-loops) uses both names for the same parameter.