The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Simulators >> Circuit Simulators >> voltage controlled cap
https://designers-guide.org/forum/YaBB.pl?num=1216113653

Message started by timmy38 on Jul 15^th, 2008, 2:20am

Title: voltage controlled cap
Post by timmy38 on Jul 15^th, 2008, 2:20am

Hi
I'm looking for some info about how to use the voltage controlled current source vccs of the cadence analoglib as a voltage controlled capacitor. Is there a way to use it with equations such as C=C0/sqrt(Vctrl) ?
I looked in the Analoglib Reference Guide but there are no information about that.
thanks

Title: Re: voltage controlled cap
Post by Ken Kundert on Jul 15^th, 2008, 7:30am

In general you are much better off using Verilog-A for this kind of thing. A process for doing that is described in www.designers-guide.org/Modeling/varactors.pdf.

-Ken

Title: Re: voltage controlled cap
Post by buddypoor on Jul 15^th, 2008, 7:54am

Hi Timmy,

in general it should be possible also in an analog circuit simulation program to model such a behaviour.
Question: Should it be (1) a real device which can be built or (2) only a behavioural model for simulation purposes ?
To (1): At first, an active capacitance multiplier using an opamp has come into my mind. In such a case, one of the resistors determining the multiplication factor has to be controlled by an external voltage.
However, an additional complication is the required square root relationship.
To (2): Something like a voltage controlled current source with a frequency dependent current should be realizable. However, I think it gives only a grounded capacitor. Is that a problem ?

Title: Re: voltage controlled cap
Post by timmy38 on Jul 15^th, 2008, 8:50am

Hi
Thanks for the link Ken.
This is actually for a behavioural model only used in simulation, so a voltage controlled current source should do. I tried to do it with the analoglib vccs but didn't quite understood how it works. Could you help me?

Title: Re: voltage controlled cap
Post by Ken Kundert on Jul 15^th, 2008, 10:53am

I am trying to help you. I recommend that you read http://www.designers-guide.org/Modeling/varactors.pdf and then use Verilog-A. You will likely save yourself a lot of trouble if you do.

-Ken

Title: Re: voltage controlled cap
Post by buddypoor on Jul 15^th, 2008, 2:00pm

timmy38 wrote on Jul 15^th, 2008, 2:20am:

...... Is there a way to use it with equations such as C=C0/sqrt(Vctrl) ?

Hi timmy,

attached please find a pdf document showing a schematic which I just have simulated with ORCAD/PSpice. This circuit with an analog behavioural model of a voltage controlled capacitor using a VCCS meets exact your requirements. The circuit constitutes a simple RC filter with a cutoff at 1 kHz. You can vary this frequency via Vc with a squareroot function - as desired. However, I don´t know if it is possible with your program as well. But it works.
Regards

Title: Re: voltage controlled cap
Post by Geoffrey_Coram on Jul 16^th, 2008, 4:26am

Wow, you guys really have a stubborn streak! Ken was trying to help you, and that document about modeling varactors also gives some hints on bad formulations that can cause convergence problems. Verilog-A is a language for writing what you want for simulation, I don't know what you think it is ...

Anyway, your model needs to be written in terms of charge (see the document for why!), and would look like this:

Code:

`include "discipline.h"
module timmy(t, b);
inout t, b;
electrical t,b;
parameter real C0 = 1p from (0:inf);
real charge;

analog begin
charge = 2 * C0 * sqrt(V(t,b));
I(t, b) <+ ddt( charge );
end
endmodule

Note that capacitance (for a (nonlinear) capacitor is dQ/dV, so this model has the dependence you asked for.

Wasn't that simple?

Title: Re: voltage controlled cap
Post by timmy38 on Jul 16^th, 2008, 5:46am

Yes thank you guys for the help, Ken's document was very helpful.
I'll try to model it in Verilog A, I'll let you know if I manage to do it or if I have some other problems because I'm a beginner in this language.
Bye then.

Title: Re: voltage controlled cap
Post by timmy38 on Jul 16^th, 2008, 5:59am

Thanks also for the file buddypoor, but I expect to simulate my model with spectre in Cadence, so I think that to model it with Verilog A is a better solution because I can't find informations about the vccs in Cadence. Thanks for bothering anyway.