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Design >> High-Speed I/O Design >> CDM ESD failure
https://designers-guide.org/forum/YaBB.pl?num=1216120016

Message started by sajinvm on Jul 15^th, 2008, 4:06am

Title: CDM ESD failure
Post by sajinvm on Jul 15^th, 2008, 4:06am

Hi all, I have attached a general ESD protection circuitry. The primary ESD is for HBM protection and secondary ESD is for CDM protection. I have the following doubt in CDM.

1. From the figure, i understand that the CDM ESD current will come from the pad and the secondary ESD protection circuit will take that current to vdd or vss. How the CDM current can come from pad? It should be coming from the core, because it is the discharge from the core as far as i understand.

Can somebody please clarify this?

Title: Re: CDM ESD failure
Post by loose-electron on Jul 15^th, 2008, 6:04pm

your secondary ESD should be tied to the same power and ground as the receiver circuit

you are trying to limit the Vgs of the transistors there.

There shoud also be limiter between power/ground supply rings as well.

Title: Re: CDM ESD failure
Post by sajinvm on Jul 15^th, 2008, 9:14pm

Hi , Thank you very much for the reply. So my main doubt is in the path of CDM ESD discharge. Where it will start ?

Title: Re: CDM ESD failure
Post by loose-electron on Aug 3^rd, 2008, 3:50pm

Hers a good description:

http://www.siliconfareast.com/esdmodels2.htm

The CDM model is all about the discharge of a chip body to ground, instead of a capacitive charge buildup outside the chp being discharged into the chip.

Title: Re: CDM ESD failure
Post by Geoffrey_Coram on Sep 29^th, 2008, 8:19am

And don't get too hung up about which direction the current goes (to/from the pad) -- recall that ESD testing is done for both polarities, and for CDM, the tester will make contact with one pin/pad, so the current has to flow through there.

Title: Re: CDM ESD failure
Post by Anbu on Oct 13^th, 2008, 12:56am

Hello Sajin,

As I understand, Primary ESD device will discharge the CDM ESD current from the CORE to PAD. This discharge current through the supply rails from CORE to the PAD will build considerable voltage across the supply rail resistance, which in turn apprears at the Gate of the Input section. Here the role of Secondary ESD is to discharge that voltage back to the supply rails and to the PAD maintaining a safe voltage at the input gate oxide.

Hence Primary ESD is to discharge the ESD current and Secondary ESD is to maintain low voltage across the Input gate oxide. Hope this helps you.