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https://designers-guide.org/forum/YaBB.pl Other CAD Tools >> Entry Tools >> Using verilogin https://designers-guide.org/forum/YaBB.pl?num=1221685570 Message started by dinac on Sep 17th, 2008, 2:06pm |
Title: Using verilogin Post by dinac on Sep 17th, 2008, 2:06pm Hi all, I am trying to do a co-simulation of my control logic for my ADC. I want to verify my Flow. i am new to mix simulation. I wrote a vhdl code for my control-logic and got a gate-level verilog.Netlist of my design, using standard-cell '.lib' or '.db' format. And now i am trying to parse this Netlist through ' verilogin '. and would be simulation with the other analog parts of my ADC. The 'Reference Library' in verilogin? is this the same standard-cell '.db'\'.lib' file? because when i tried to define this in cds.lib, i find no cells in the ' Library Manager '. is this Ok? Even though I discard this and try parsing the Netlist. i get some errors: VerilogIn: *W,31 => Module X in FSM_file not defined.Module FSM_file will be imported as functional. VerilogIn: *W,101 => Could not find symbol master for instance XY .Functional view won't have this instance. Please Help me .. Thanks........ |
Title: Re: Using verilogin Post by bernd on Sep 18th, 2008, 1:35am Quote:
NO this is not OK, you need a Cadence DFII library of your standard cells for importing your Verilog Gate Level, this is a different library format as *.db or *.lib. You usually get the Cadence DFII library form your standard cell vendor or you have to create the Cadence DFII library, cell views and netlist properties, yourself. No that trivial for a beginner. * |
Title: Re: Using verilogin Post by dinac on Sep 18th, 2008, 6:32am Hi bernd / all, Thanks for your reply. I guess i solved it 1. Reference Library "CDK" 2. -V option i provided the link of the standard-cell file in verilog format. ".V" I found few errors, mentioning the verilog " Verilog definition for module AND2 was not found. Using lib 'techlib' cell 'AND2' view 'symbol' as its symbol. But i guess I could discard this. Thanks a lot Again cheers dinac |
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