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Design >> High-Speed I/O Design >> The capacitive load of transmission
https://designers-guide.org/forum/YaBB.pl?num=1224150675

Message started by dandelion on Oct 16^th, 2008, 2:51am

Title: The capacitive load of transmission
Post by dandelion on Oct 16^th, 2008, 2:51am

Hi

I am designing a block whcih will drive a transimission (50cm long) and a FPGA chip.The block will works in 1.25G.

I wonder, in simulation, how to define the load? especially the capacitive load? 5pF is enough?

BTW, the output of the block is PECL.

Thanks

Title: Re: The capacitive load of transmission
Post by loose-electron on Feb 15^th, 2009, 1:01pm

You need to define the PCB trace and width, min/max criteria. With that in hand you can then get from a number of sources (Google PCB dielectric capacitance) the capacitance limitations for the traces. If you are doing high frequency design (above 10MHz for the sake of discussion) you may want to do a more complete PCB trace model that includes distributed trace RLC elements and transmission line models.