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Design Languages >> VHDL-AMS >> need vhdl code
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Message started by nave4u on Nov 4^th, 2008, 1:52am

Title: need vhdl code
Post by nave4u on Nov 4^th, 2008, 1:52am

hi every one

i got problem in writing a code for small architecture can any one help me out...the problem is

i have one 4-bit registe as one of the input to a 2:1 mux and other input is bit '1' and i have a selection line which will select either of input....if selection line is ' 1' then the output of mux is lsb of 4-bit regester and if the selection line is '0' then the output of the mux is '1' which is second input of the mux.....and for every clock cycle i need to shift the 4-bit register to the right and it should be done in 3 cycle till all the bits in the regester get selected...

plzzzz help me out from this problem as soon as possible....