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Design >> High-Speed I/O Design >> What is the relationship between chip-level and system-level in ESD
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Message started by flyfeng on Nov 16^th, 2008, 1:21am

Title: What is the relationship between chip-level and system-level in ESD
Post by flyfeng on Nov 16^th, 2008, 1:21am

Dear all,
I have been in trouble with my design work about esd for long times.I eagerly want to know that what is the relationship between
chip-level and system-level in ESD.What should I consider about when designing an IC ESD architecture to slove the system-level ESD's problem.
As we all know,the aim to design an IC is to apply with a system and the attention what clients pay is the system-level ESD,such as the ESD test on the mobilephone. IEC61000-4-2 is usually followed.
We usually add capacitances outside the key pin of the key ic,but we
don't know is there any methods to solve this problem.
Would any ESD experts can help me?
Thanks a lot!

Title: Re: What is the relationship between chip-level and system-level in ESD
Post by Luckyday on Nov 16^th, 2008, 6:17pm

I am an EMI engineer from China, and I also deal with ESD issue. In my opinion , the chip-level should be higher than system-level in ESD, and some ESD protection chip should be used to solve ESD problems,just like TVS and so on.
I meet some ESD issues that some IC chip was destoryde because of ESD problems.
I hope it will be helpful.
Thank you.

Title: Re: What is the relationship between chip-level and system-level in ESD
Post by SRF Tech on Nov 18^th, 2008, 11:13pm

Hi everyone, its been a while since I logged in, but this is a good question.

There is a big difference between designing for system level ESD (that is generally tested with IEC 61000) versus chip level ESD such as HBM, CDM or MM.

A very crude summary of the test

Test Current Pulse Duration
CDM (500V) 5-7 Amps <1-3nS
HBM(2kV) 1.3 Amp 400-800nS
MM (200V) ~3A 50-200nS
IEC61000(8kV) >20A ~200nS

This is a very crude table and not based on any official spec, just general waveforms that can appear for a given test on a variety of DUT's. But it highlights a significant difference between IEC and normal IC level ESD tests. The biggest difference is current peaks, as well as the waveform shape which I will not discuss here, but the IEC has 2 primary peaks, whereas other tests do not.

Another difference is pin and current paths. In an IEC 61000 stress on a system, basically a single pin is zapped by contact or air discharge...the returning current path is generally some long ground strap between the system and the gun. This path has never been properly spec'd and creates massive variations in IEC testing between setups, even for the same system.

ESD pin combinations for IC components are very well defined and controlled. HBM and MM are two pin tests (or a pin to group stress). CDM is a single pin stress, but on a part that is floating and there is no DC level return path between the part and its environment.

So what is my purpose in this:

1. Designing for a specific chip level stress (such as HBM 4kV) and trying to correlate it to some IEC level (say 8kV) is a mistake.
DO NOT ATTEMPT TO CORRELATE IC ESD DESIGN TO SYSTEM LEVEL PERFORMANCE< ESPECIALLY FOR A CRUDE AND INCONSISTENT TEST SUCH AS IEC61000 WITH A GUN. Its a mistake.
So do not fall into the trap of thinking, if I design for 4kV HBM, I should handle 2kV or 4kV or 8kV IEC...such an assumption is a major error.

2. If you want a pin or group of pins on a part to pass an IEC stress, you need to design the ESD protection to explicitly deal with the currents and waveform of an IEC stress...you also need to spec ground pins on your part and how they should be connected to the system to control the IEC current return path/impedance.

3. DO NOT ATTEMPT TO DO ESD TESTING, SUCH AS HBM WITH AN ESD GUN EVEN IF IT SAYS "HBM WAVEFORM TIP". It is very wrong and the manufacturers should be held accountable for marketing it but they are not. (ok you didn't ask for this but I threw it in anyways. :) )

So your solution is, design an extremely robust ESD protection scheme on-chip, explicitly targeting an IEC 610000 waveform....or....design the system to handle the event and thus protect the IC pins. Beware of discrete ESD/IEC marketed products ( a popular one right now are HDMI ESD protection chips), they market that the parts can withstand IEC 61000 to 16kV and so forth, but it does not mean they will protect your chip at IEC 16kV.

Also, they market super low capacitance, but look closely at the specs, generally the capacitance marketed is differential capacitance between pins, not load capacitance to ground which can kill your signal integrity on high speed lines. (that number is generally buried in the specs and is not always that great). Ok another tip you didnt ask for.

Hope this long post helps you.

Stephen