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https://designers-guide.org/forum/YaBB.pl Other CAD Tools >> Entry Tools >> schematic to Verilog-A https://designers-guide.org/forum/YaBB.pl?num=1228822533 Message started by rajdeep on Dec 9th, 2008, 3:35am |
Title: schematic to Verilog-A Post by rajdeep on Dec 9th, 2008, 3:35am Hi all, Is there a way to convert a schematic into a structural Verilog-A code. Say, I connect 3 blocks A, B and C in some way using Cadence Schematic Editor. Now is it possible to translate this scheamtic into an equivalent verilog-A view? The inbuilt view translator doesnt work! One easy way cud be translatng the spectre netlist into an equivalent verilog-A netlist using soem scriptng, but the script is failing at time...so in the lookout for a robust code or available tool for this! Otherwise, it is abs nightmare to wire those big netlists manually! Rajdeep |
Title: Re: schematic to Verilog-A Post by pancho_hideboo on Dec 9th, 2008, 4:02am You can do such netlisting by using NC-Verilog or Verilog-XL integration in ADE. This means netlisting by netlister for Verilog-D. But you have to force netlister to stop before transistor level. Here you have to specify any virtual stop view for lowest blocks which include transistor, resistor, etc. |
Title: Re: schematic to Verilog-A Post by Andrew Beckett on Jan 2nd, 2009, 11:42pm Or you can use the cell-based Verilog-AMS netlister to do this. If you use Tools->AMS->Netlist in the CIW, you can specify a cellView. It will create the netlist within the cellView directory, so you can find it there... This doesn't need any switch/stop view setup (because it only netlists a single cellView), but if you have primitive devices in the schematic, it would need ams simInfo in the CDF (this isn't needed for blocks though). Regards, Andrew. |
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