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Design >> High-Speed I/O Design >> Driver impedance, slew rate, loading and signal integrity
https://designers-guide.org/forum/YaBB.pl?num=1229955438

Message started by neoflash on Dec 22^nd, 2008, 6:17am

Title: Driver impedance, slew rate, loading and signal integrity
Post by neoflash on Dec 22^nd, 2008, 6:17am

Assume we are designing a CMOS DDR3 driver, user requested different output driver impedance to cover different capacitive loading.

For example, 18 DRAM units may require 20ohm output impedance while 36 units may require 12ohm output impedance.

I'm curious that if whether we should use a faster slew rate for heavy capacitive loading, or use a slower slew rate?

Fast edge rate will incur more reflection, any consideration on this effect? Please recommend some literature if any, thanks.

Title: Re: Driver impedance, slew rate, loading and signal integrity
Post by SRF Tech on Jan 2^nd, 2009, 8:45pm

Hi Neo,
I would first say that what you are looking for is to ideally have a precise slew rate to meet your timing requirements, that is constant for either large or small capacitive loads.

I would not try to adjust slew rates, but rather drive currents so that slew rates are consistent over all operating conditions (and that they meet your timing specifications for the DDR3 standard). That should be your goal.

Let me know if I misunderstand what you are asking

Stephen

Title: Re: Driver impedance, slew rate, loading and signal integrity
Post by shashi.kiran on Jul 9^th, 2009, 4:26am

I completely agree with stephen , since DDR3 driver working around 800mhz it would not be suggestive to slew it and not meet the DDR3 timing spec. However , if ur worrying abu signal integrity its always suggestive to skew the driver and to have better calibration for termination..etc.