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Modeling >> Behavioral Models >> PLL o/p phase noise plot
https://designers-guide.org/forum/YaBB.pl?num=1230894262

Message started by trond on Jan 2^nd, 2009, 3:04am

Title: PLL o/p phase noise plot
Post by trond on Jan 2^nd, 2009, 3:04am

Hello,

I have a behavioral model of a fractional N PLL (PFD,CP,LP,VCP, Divider, Sigma Delta Modulator). I use the model to obtain the periods at the output of the PLL which I use to calculate the phase noise.* All models used are ideal and have no additional noise sources.

My question is regarding the phase noise plot at the o/p of the PLL.
As well known each block will have a noise transfer function to the o/p which is shown in the figure. Since only the SDM contributes qunatization noise which modulates the PLL o/p frequency I would expect the phase noise plot obtained by the Matlab script to be that of the modulator noise only, as everything else is ideal.

However, the phase noise plot resembles more that of the total noise plot shown in the figure. I don't understand why I do not obtain a plot showing the quantization noise of the SDM only, which is shaped by the NTF of the SDM and the PLL loop filter.

The only reason I can think of is because the model is a closed loop model and the individual plots shown in the figure are essentially from an open loop.

Can anyone help me understand this trivial question?

Thanks,

* See paper "Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers" on this website, page 45.

Title: Re: PLL o/p phase noise plot
Post by peng on Jan 20^th, 2009, 7:56pm

Due to my experience, if other blocks are idea, only the quantization noise from the sigma delta modulator would show up at the output of the synthesizer. How did you implement your synthesizer? In which environment?

Title: Re: PLL o/p phase noise plot
Post by walkingsun on Feb 12^th, 2009, 9:16pm

I have same problem.
The every block is ideal. So, the phase noise should only be the QNoise.
But at the low frequency, about 100KHz-1MHz, the phase noise is too large.

I don't know why

Title: Re: PLL o/p phase noise plot
Post by trond on Feb 13^th, 2009, 2:41am

I had started a similar post here:
http://www.designers-guide.org/Forum/YaBB.pl?num=1231252540
as at the time I thought it was more of a general phase noise question.

Writing phase domain models yielded accurate results as Aigneryu in the other post pointed out. Still, time-domain models should give also the accurate results!

It must have something to do with tolerances. I had tightened the tolerances on the simulation (i.e. reltol, iabstol, maxstepsize and so on) but would only see a slight improved.
However, after replacing one of the models with their transistor level counter part (simulation took somewhat longer to run) the results all of a sudden where as expected. Which would again point towards simulation accuracy.

Title: Re: PLL o/p phase noise plot
Post by walkingsun on Feb 16^th, 2009, 5:23am

Could you show me the simulation results, with some real model?

Title: Re: PLL o/p phase noise plot
Post by trond on Feb 17^th, 2009, 1:53am

Shown is an all verilogA simulation (red). As you can see lots of low frequency "noise". Not sure how real this is. I have not tried running multiple simulations and averaging the results. This might help.

Same setup but with a gm-block and reference voltage generation block replaced by their transistor level counter parts (blue).

Title: Re: PLL o/p phase noise plot
Post by emad on Mar 17^th, 2009, 4:27am

If all blocks are ideal then what you see is a numerical artifact that depends on your simulation methodology. For example, how did you implement your PFD? Is it event-driven or strobed? What is the sampling rate of your loop filter? How is the VCO modeled? Is it phase domain or time domain? Note that the fact that you run a transient simulation does not mean that your VCO model is time-domain based.

Digital simulation of analog components can be very tricky because there is implicit quantization of everything. This may render the loop open for a short amount of time and makes your noise shoot up. There is also quantization noise floor that results from time quantization. A smaller time step should enhance that at the expense of a longer simulation time.

Cheers!

Title: Re: PLL o/p phase noise plot
Post by emad on Mar 18^th, 2009, 5:59am

Mixing event-driven models with storbed models is not an easy task. For example, if the PFD is event-driven and the loop filter is strobed, a very high sampling rate for the filter is required because otherwise it can miss events that happen between two samples of the loop filter. The fact that the loop filter is narrow band doesn't really help. Accordingly, the PLL is acting as if it is open and numerical noise shoots up in the presence of a sigma delta modulator and shows a behavior that is similar to what you show.