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Simulators >> Logic Simulators >> Passing bit width in module parameter instance definition in nc-verilog
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Message started by SG on Feb 4^th, 2009, 10:33am

Title: Passing bit width in module parameter instance definition in nc-verilog
Post by SG on Feb 4^th, 2009, 10:33am

Hi,

I have been using verilog-xl so far and have got my code compiled in the format where I use the same module with different bit-widths and get it compiled.

For eg,
quantizer #(32,16) quant1(out,in)

I now need to generate some annotation files using nc-verilog and hence, when I compile the same in it, it gives me an error, with the "#(32,16)" part: Too many module instance parameter definitions.

Is it possible to make nc-verilog read the above statement without having several copies of the same module in my code ?

Thanks for you help,
Shubh.