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Modeling >> Behavioral Models >> voltage limited current controlled current source (cccs)
https://designers-guide.org/forum/YaBB.pl?num=1234822036

Message started by Ari on Feb 16^th, 2009, 2:07pm

Title: voltage limited current controlled current source (cccs)
Post by Ari on Feb 16^th, 2009, 2:07pm

I wish to build voltage limited current controlled current source using Verilog A module, to model ideal current source which is limited to supply voltage when current sink has high resistivity.

I tried using the following code, but it fails to converge for high impedance load on Isink.

any ideas how to implement such a source?

Code:

I(sink,src) <+ gain*I(ctrl_p,ctrl_n);

if (V(src)>vclip) begin
$strobe("cccs_vlimit clipping voltage as it is=:%g and clip value is:%g\n",V(sink,src),vclip);
I(sink,src)<+ max(0, gain*I(ctrl_p,ctrl_n) + gm_nom*(V(src)-vclip));
end //if

Title: Re: voltage limited current controlled current source (cccs)
Post by Peruzzi on Feb 16^th, 2009, 3:27pm

Ari,

Try combining with exponential functions for limiting. It will be continuous in all its derivitives and will behave better.

Bob Peruzzi