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Design >> Analog Design >> pole zero doublet
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Message started by raja.cedt on Feb 25^th, 2009, 8:28pm

Title: pole zero doublet
Post by raja.cedt on Feb 25^th, 2009, 8:28pm

hi,
can any body please explain how to get intuitive feeling about doublet,means by looking at the circuit is there any way to predict pole-zero doublet.Apart from the settling effect ,is there any effect on system performance?

Thank you,
Rajasekhar.

Title: Re: pole zero doublet
Post by Visjnoe on Feb 26^th, 2009, 10:51am

Yes, you can intuitively assess whether or not a circuit has a pole-zero doublet.
Look for 2 parallel signal paths from input to output. When one signal path has a pole that the
other signal path does not have, a pole-zero doublet will arise.

Regards

Peter

Title: Re: pole zero doublet
Post by thechopper on Feb 26^th, 2009, 5:53pm

I agree with Peter. In addition consider the particular case of 2 parallel signal paths intended to have the same pole but with some degree of mismatch - say - in one branch´s capacitor.
Mismatch of (intended identical) poles in a differential circuit is one example of this.

Regards
Tosei

Title: Re: pole zero doublet
Post by raja.cedt on Feb 26^th, 2009, 9:45pm

Thanks for your valuable reply.I think in differential pair pole zero will come because of parallel path,but those are 2X distance,so does it impact any settling?Is there any other circuits which will give double(give me some examples).And more over is there any other impacts on time response other than settling?
Thank,
Rajasekhar.

Title: Re: pole zero doublet
Post by Berti on Feb 27^th, 2009, 1:15am

There is a famous paper from R. Meyer and P. Gray about this issue:
" Relationship Between Frequency Response and Settling Time of Operational Amplifiers".

Cheers

Title: Re: pole zero doublet
Post by thomasross20 on Feb 27^th, 2009, 8:36am

Yes, that is an excellent paper, Berti.
Check out Klas Bult's famous paper, something about a fast settling 90dB amplifier...
Basically another circuit which involves doublets if you're not careful is that of a gain-boosted amplifier. Just make sure the UGBW of the gain-boost amps is greater than the -3dB freq of the main amplifier.

Title: Re: pole zero doublet
Post by skywalker_1 on Mar 3^rd, 2009, 4:44am

you can even refer one book by Sansen "Analog design essentials" He took example of Current mirror load in opamp for doublet generation

Title: Re: pole zero doublet
Post by nobody on Mar 3^rd, 2009, 6:31pm

I have a question and was wondering if ac simulation can find the effect of pole-zero doublet. Thanks.

Title: Re: pole zero doublet
Post by raja.cedt on Mar 3^rd, 2009, 10:23pm

hi,
i think it is always better to check doublet effect in time response,because in ac simulation u may miss doublet if they are very close and if step is large of course with transient response also same will happen if we are not care....

Title: Re: pole zero doublet
Post by nobody on Mar 3^rd, 2009, 10:33pm

I go with Rajasekhar and what he said is pretty much like what I heard about the effect of pole-zero doublet in AC simulation. Thanks again.

Title: Re: pole zero doublet
Post by raja.cedt on Mar 4^th, 2009, 12:08am

hi,
i am sorry to ask this question but i can't.I calculated transfer function for gain boosted amplifier,and from that i to know that there is doublet at the ugb of the error amplifier,is there any way to predict this with out doing lot of math ,even i don't want the location of the doublet,but at least how to predict that there is a doublet.Thanks for your valuable time.
Regards,
Rajasekhar.

Title: Re: pole zero doublet
Post by vivkr on Mar 5^th, 2009, 2:42am

Hi,

Indeed, there is a very simple way to predict that there is a doublet without doing any math at all. I assume that you have not read the classic paper by Bult and Geelen ("A fast settling CMOS Opamp for SC Applications with 90 dB DC Gain" which appeared in the JSSC, Dec. '90 issue).

Look at the gain profile of a gain-boosted amplifier for the case where the -3dB bandwidth of the main amp is f0, and for the boosting amp f1, where f1 << f0 (as a simple example). Say the main amp has gain G0, the boosting amp G1, both in dB.

Now the gain at DC is G0 + G1, and stays so until f1, where it starts to drop by 20 dB/dec, until it reaches f0 upon which it becomes constant at G0 dB until you reach f0.

So, the gain first drops and then it becomes flat, hinting that a pole is followed by a zero. That's all there is to it really.

Regards,

Vivek

Title: Re: pole zero doublet
Post by raja.cedt on Mar 13^th, 2009, 10:48pm

hi vivkr,
Thanks for your advice,i read the paper and finally i got one basic doubt.
1.In any feedback loop all blocks inside loop should be as fast as possible when compared with the overall loop,for example i am designing pll,inside all charge pump amps are i am designing 10* faster than loop,other wise it will effect loop performance.But in this paper the conclusion is added amplifier's UGB should be less than the overall amplifier.Can u please explain where i am getting wrong?
Thanks,
Rajasekhar.

Title: Re: pole zero doublet
Post by vivkr on Mar 16^th, 2009, 12:33am

Hi Rajshekhar,

As far as I remember, the paper also states that the auxiliary amp's bandwidth should be higher than the overall loop bandwidth (which is also the logical conclusion you have drawn), and so I see no contradiction. Maybe you have misinterpreted something.

Regards,

Vivek

Title: Re: pole zero doublet
Post by zzhang on Mar 19^th, 2009, 11:52pm

i have design a gainboost amp, the main amp is telescopic and the aux amp is foled. the pole-zeros are all real number when the three amps simulated seperately. but when i simulted the gainboost one, the first two doublets which were arised by two aux ampa are complex numbers. I doubt how the complex numbers doublts arise,why they weren't the real numbers doublts.

Title: Re: pole zero doublet
Post by vivkr on Mar 20^th, 2009, 12:40am

zzhang wrote on Mar 19^th, 2009, 11:52pm:

What else do you expect? The auxiliary amps after all are now in closed-loop.

Vivek

Title: Re: pole zero doublet
Post by Sarig on Mar 20^th, 2009, 5:20am

Simple answer:
when you start playing with tricks to fix your PM by adding zeros or compensation Ideas then problmes start and if yo usee that your phase is not acting like 1st / 2nd order but aslo rise sometimes then you got some doublet issue.
Erez

Title: Re: pole zero doublet
Post by Manas on Feb 18^th, 2010, 11:08pm

raja.cedt wrote on Mar 3^rd, 2009, 10:23pm:

How you will see the doublet effect from the time response ??

Title: Re: pole zero doublet
Post by Berti on Feb 18^th, 2010, 11:33pm

Manas, you will find the answer to your question in the following paper:

@article{KamathJSSCDec74,
B.Yeshwant Robert G.Meyer and Paul R. Gray
Relationship Between Frequency Response and Settling Time of Operational Amplifiers
IEEE of Solid--State Circuits
1974
volume = "sc-9",
number = "6",
month = "December",
pages = "347-352"
}