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Modeling >> Semiconductor Devices >> cgd modeling in bsim4
https://designers-guide.org/forum/YaBB.pl?num=1237972274

Message started by kanan on Mar 25^th, 2009, 2:11am

Title: cgd modeling in bsim4
Post by kanan on Mar 25^th, 2009, 2:11am

Hi,
Is the gate-drain metal-poly fringing cap modeled in BSIM4? I am running calibre and it seems to be extracting that cap and I am wondering whether this is a case of double counting?

Title: Re: cgd modeling in bsim4
Post by Geoffrey_Coram on Mar 25^th, 2009, 5:43am

BSIM4 has parameters to model gate to drain overlap capacitance, as well as the CF parameter to model fringing capacitance -- but you have to check your model card for the mos device to see if the foundry zeroed those out with the expectation that you'd extract values -- note that CGDO and CF have computed defaults, so if they're not in the model file, you can still get a non-zero value.

Title: Re: cgd modeling in bsim4
Post by kanan on Mar 26^th, 2009, 2:01am

Thank you Geoffrey!
This query came from the fact that while designing a high speed VCO, the post-layout extraction is throwing up a lot of CC caps (Cdg, Cds). The values are of the order of 5fF which create enough trouble at that speed.
Now the transistors themselves are quite bare and I don't believe there is anything else in layout I can do to get rid of them.
I am not sure if these capacitances are real or a case of "double-counting" by calibre.

Any comments?

Title: Re: cgd modeling in bsim4
Post by Geoffrey_Coram on Mar 26^th, 2009, 6:11am

Your description makes it sound like the 5fF from Calibre is too much, which has nothing to do with possible double-counting.