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https://designers-guide.org/forum/YaBB.pl Simulators >> System Simulators >> Complex Analog/RF/DSP IC design tool/flow https://designers-guide.org/forum/YaBB.pl?num=1238242506 Message started by currant on Mar 28th, 2009, 5:15am |
Title: Complex Analog/RF/DSP IC design tool/flow Post by currant on Mar 28th, 2009, 5:15am Hi, I've a task of design complex ICs, which will use in communication systems like TETRA, and consists of some RF part, bandpass SD-ADC and some digital filters. And main problem - full top-down design, preferable, without problem connections betwen tools. Especialy, I guess problems in hierarchical design, when I will need verify circuits of blocks in system bench. Could anybody help me about preferable set of tools, one of which is Cadence IC? Cadence very good design environment while one works with lumped components ( as is on my design). But I worry about system simulation, because spectreRF suffer from hidden states, that are being in FIR filters for example. I am thinking about ADS with Dynamic Link, but don't know how system simulation (Ptolemy) will work with circuits from cadence. What kind of problem can I meet in this couple of tools? Does anybody create complex RFIC by this way or may be one another flow? |
Title: Re: Complex Analog/RF/DSP IC design tool/flow Post by pancho_hideboo on Mar 28th, 2009, 5:27am I'm now using ADSsim, Ptolemy and NCSim for this purpose. I don't use Cadence AMSD. Here I use Verilog-AMS of ADSsim to do cosimulation with NCSim. And I use many models which are built by FDD and system model library even in Cadence Composer schematic. Agilent recommended users to use WTB in RFDE if they want to use Ptolemy models in Cadence Design Environment. But I don't use WTB. Instead I use dynamic link if I have to use Ptolemy models. Although I also have MATLAB/Simulink, I don't use it for cosimulation with continous time domain simulator. Since I have incisive link of Simulink, I do cosimulation between Simulink and NCSim. currant wrote on Mar 28th, 2009, 5:15am:
Ptolemy models can be available as WTB in Cadence Design Environment. You can also use them by Dynamic Link where master analysis controler is Ptolemy and slave analysis is ADSsim. As far as you use Verilog-AMS models, hidden states problem exist also in ADS. But ADS have FDD modeling ability. If you write own models by this FDD, you can use them even in envelope analysis. And big advantages of ADS is that ADS has rich system model library which are available even in envelope analysis. Since they are available as netlist, it is easy to use them in Cadence Composer schematic. But dynamic link and RFDE are terminated in ADS2009. http://www.designers-guide.org/Forum/YaBB.pl?num=1237378629/1#1 currant wrote on Mar 28th, 2009, 5:15am:
See http://www.designers-guide.org/Forum/YaBB.pl?num=1234618137 currant wrote on Mar 28th, 2009, 5:15am:
Here you should consider following isuues. - Fast Transient Analysis without loss of accuracy - Fast Envelope Analysis - Cosimulation with Logic Simulator such as Cadence NCSim using Verilog-AMS or Verilog-D - Cosimulation with system simulator such as Agilent Ptolmey or MathWorks Simulink Instead of ADSsim, I will use Agilent GoldenGate with Verilog-AMS to do cosimulation with Cadence NCSim. Here Ptolemy models can be imported into GoldenGate. But they are limited to sink and source models now. Envelope analysis of GoldenGate is very fast. To my regret, FDD custom models and system model library are not avaliable in current GoldenGate. We can't use Verilog-AMS models which have hidden states if we will use envelope analysis. However for transient analysis, we can use Verilog-AMS models which have hidden states. So I want to introduce BDA's FastSpice which is possible to do cosimulation with Cadence NCSim. http://www.designers-guide.org/Forum/YaBB.pl?num=1183646486/11#11 So simulators in my environments are : - Agilent ADSsim (to be terminated) - Agilent Ptolemy - Agilent GoldenGate (to be introduced instead of ADSsim) - Cadence NCSim - BDA's FastSpice (want to introduce) If you prefer Cadence Tools, use Cadence AMSD. Here Agilent Ptolemy models can be imported into Cadence AMSD. And you can do cosimulation with MathWorks Simulink. - Cadence AMSD(MMSIM and NCSim) - MathWorks Simulink - Agilent Ptolemy |
Title: Re: Complex Analog/RF/DSP IC design tool/flow Post by Visjnoe on Mar 28th, 2009, 6:45am The tool suite from Agilent is complete, but rather expensive. Most FastSPICE simulator can handle a combination of Verilog/VHDL/Verilog-AMS/SPICE so that is the way to go for your full-chip simulation. Most of these are however limited to transient analysis. If you want to avoid these problems, you can simulate the analog portion using your tool of choice and write the output of the ADC to some temporary file which you take as input of your digital portion. Regards Peter |
Title: Re: Complex Analog/RF/DSP IC design tool/flow Post by pancho_hideboo on Mar 28th, 2009, 6:53am Visjnoe wrote on Mar 28th, 2009, 6:45am:
Visjnoe wrote on Mar 28th, 2009, 6:45am:
But Cosimulation of Nanosim and VCS is very lacking in accuracy for RF applications. Cosimulation of HSIM and VCS might be useful for RF applications compared to NanoSim to some extent. |
Title: Re: Complex Analog/RF/DSP IC design tool/flow Post by currant on Mar 28th, 2009, 6:56am Many Thanks, pancho_hideboo! You are first one, who answer this question so in detail! For my regret, I don't know what is FDD (maybe frequency domain)? There is one problem. Circuit designers works in Cadence and uses spectreRF analysis, but I have to take their circuits and try to verify in my system model, and I until now don't find teqnique to do this. And it is seems, that Cadence Virtuoso+Dynamik Link+Ptolemy is most seamless method to simulate analog/RF circuits in system-level model environment with minimal loss of accuracy. And unique feature of Ptolemy - uses, at the same time, three type of analysis. In this moment I talk mainly about Analog/RF not digital (which I wanted create on Verilog-A/AMS until now). But there are two bad news: about Dynamik Link and problems with hidden states in Ptolemy. I thought about MATLAB, but it allows to work only on Verilog-A model level, and there is no way to simulate transistor level circuits. Is there not enough use only Ptolemy source/and sink in GG flow, so co-simulation with Ptolemy would be realized through files? Sorry for my Russian English ). |
Title: Re: Complex Analog/RF/DSP IC design tool/flow Post by currant on Mar 28th, 2009, 7:32am I meant: SDF/TSDF, Tran, Envelope, as I undestand: system is simulated by DataFlow controller, but in model one may uses blocks with internal Tran or Envelope controller. About MATLAB. As I know, MATLAB can work with Verilog-A models, may be I wrong. s-parameters is valid mainly for RF linear blocks, but how could I simulate in MATLAB OPAMP with distortions and without creating top-level model for the circuit ? I thought, that in Ptolemy I could be, via Dynamik Link, simulate OPAMP circuits by Tran Analys in system, that is simulated by DataFlow analys. am I wrong? |
Title: Re: Complex Analog/RF/DSP IC design tool/flow Post by currant on Mar 28th, 2009, 8:00am Yes, I have no practic in simulation with Ptolemy. Could You breifly explain what can I expect from co-simulation cadence analog/RF circuits with Ptolemy (or give some links for reading)? Sorry, of course, I meant Simulink. From Ptolemy datasheet: In ADS Ptolemy, a complex system is specified as a hierarchical composition (nested tree structure) of simpler circuits. Each subnetwork is modeled by a domain. A subnetwork can internally use a different domain than that of its parent. In mixing domains, the key is to ensure that at the interface, the child subnetwork obeys the semantics of the parent domain. Thus, the key concept in ADS Ptolemy is to mix models of computation, implementation languages, and design styles, rather than trying to develop one, all-encompassing technique. |
Title: Re: Complex Analog/RF/DSP IC design tool/flow Post by pancho_hideboo on Mar 28th, 2009, 8:21am It seems that you can't arrive at enough level to understand "Complex Analog/RF/DSP IC design tool/flow". currant wrote on Mar 28th, 2009, 8:00am:
Both Simulink and Ptolemy are classified as DT(Discrete Time) or TSDF(Timed Synchronous Data Flow) Simulator. Models of both Ptolemy and Simulink are signal flow model(not energy conservative system). On the other hand, models of Verilog-A are energy conservative system which have flow and potential. Of course you can use Verilog-A for signal flow modeling. Although Ptolemy have only fixed time step solver, Simulink have both continuous and fixed time step solvers. About performance as DT simulator, Simulink is superior than Ptolemy. Agilent might replace Ptolemy with SystemVue. currant wrote on Mar 28th, 2009, 8:00am:
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Title: Re: Complex Analog/RF/DSP IC design tool/flow Post by currant on Mar 28th, 2009, 8:33am This information, absolutely that I need. I know about RF blockset and work with Simulink . The main point in question was: How simulate transistor level circuits from cadence Virtuoso in different fom Virtuoso system simulator without translation from circuit to system set of parameters such of S param, IIP3, NF and etc. may be this is incorrect question. But now, I know set of tools, that could be use in this task and some limits of tools. Many thanks, pancho_hideboo! |
Title: Re: Complex Analog/RF/DSP IC design tool/flow Post by pancho_hideboo on Mar 28th, 2009, 8:42am currant wrote on Mar 28th, 2009, 6:56am:
Here you can also do cosimulation with Simulink. And you can also import models of SPW(CoWare SPD). On the other hand, if you use Agilent Dynamic Link, you can not use models of Simulink, although you can do cosimulation with m-files of MATLAB. currant wrote on Mar 28th, 2009, 6:56am:
currant wrote on Mar 28th, 2009, 7:32am:
In Mixed-signal systems, you need mixed analysis of following three domains. - CT(Continuous Time) ; Tran, Envelope - DT(Discrete Time) ; SDF/TSDF simulator such as Ptolemy, Simulink, SPW(CoWare SPD), SystemVue, etc. - DE(Discrete Event or Event Driven) ; NCSim, VCS, ModelSim If you use Agilent Dynamic Link or WTB, master controller is DT. If you use Agilent GoldenGate, master controller is CT. If you use Cadence AMSD, master controller is DE. |
Title: Re: Complex Analog/RF/DSP IC design tool/flow Post by DaveB on Mar 29th, 2009, 7:49pm The whole co-simulation issue is complicated by the different timescale's required. To do transistor level simulations, you need a simulation timestep that supports the interesting signal bandwiths. If you are looking at a 2 GHz system, you might want to simulate up to the 5th harmonic, so you'd want to set your simulation bandwidth to 10 MHz. However, this gives you a timestep requirement of 50 nSec. However, if you are trying to look at spectral mask performance in a transmitter, you'll need to transmit thousands of bits to get a good mask. If your datarate is 1 MBit/sec, you might need to have a simulation length of 1 mSec, or 20 million timesteps. Doing co-simulation is pretty complicated, and needs a fair amount of attention to set up so you get reasonable answers out. Dave |
Title: Re: Complex Analog/RF/DSP IC design tool/flow Post by pancho_hideboo on Mar 30th, 2009, 1:19am DaveB wrote on Mar 29th, 2009, 7:49pm:
And generally your estimation is not enough. I use time step lesser than 20psec(=1/(5*10GHz)) for 10GHz System. DaveB wrote on Mar 29th, 2009, 7:49pm:
If we use envelope analysis and both target circuit and modulation scheme are well suited to envelope analysis, time points will be largely reduced. There is important issue in transient analysis for RF system even if we use BDA's FastSpice. Time step of current commercial transient analysis iteself is single rate over whole circuits. This is true for saved data. You should save data using different time step for RF signal and IF or BB signal. Here you need sink component to capture signal at different time step. |
Title: Re: Complex Analog/RF/DSP IC design tool/flow Post by currant on Apr 14th, 2009, 1:55am Hi, pancho_hideboo. Once again, thank You for help! Now, I am using evalution version of ADS2009 (Dynamic Link still exist), and I have a question. When I try to use DynamikLink, I find some problems. For example ADSSim does't undestandt mos0 primitive. In spite of the fact that this is a simple model and doesn't use in real devices, I am worry. Did You have any problem with simulation Spectre models from real PDK by ADSSim ? Do I need to have special models for ADSSim if I use DynamikLink? And would I need special models for ADSSim, if I don't use dynamikLink and work on level of import/export netlist? Thanks! |
Title: Re: Complex Analog/RF/DSP IC design tool/flow Post by pancho_hideboo on Apr 14th, 2009, 3:41am currant wrote on Apr 14th, 2009, 1:55am:
currant wrote on Apr 14th, 2009, 1:55am:
How do you include model file in ADS schematics ? Do you surely put "netlist_include" component which specify model files in Spectre Syntax ? Show me your netlist of Dynamic Link. currant wrote on Apr 14th, 2009, 1:55am:
ADSsim can understand netlists of Cadence Spectre Syntax directly. See the followings. http://www.designers-guide.org/Forum/YaBB.pl?num=1205223090 http://www.designers-guide.org/Forum/YaBB.pl?num=1216663909 |
Title: Re: Complex Analog/RF/DSP IC design tool/flow Post by currant on Apr 14th, 2009, 3:55am I included model file via Netlist Include block. Model file was a rfModels.scs. When I comment some models (pch , nch and gaas) simulation was done. Netlist: #ifndef inc_rfExmplTrain_ne600_ADS_schematic #define inc_rfExmplTrain_ne600_ADS_schematic \ inc_rfExmplTrain_ne600_ADS_schematic ; Library name: rfExmplTrain ; Cell name: ne600_ADS ; View name: schematic define rfExmplTrain_ne600_ADS_schematic ( Pif Plo Prf ) simulator lang=spectre crf (net33 Prf) capacitor c=10n C1 (net51 0) capacitor c=1 * 0.6p C2 (net49 0) capacitor c=1 * 0.6p cif (net55 net27) capacitor c=10n clo (net39 Plo) capacitor c=10n cm (net27 0) capacitor c=4.7p L1 (net51 net33) inductor l=3n ldc (net41 net55) inductor l=10u lm (net27 Pif) inductor l=470n L0 (net49 net39) inductor l=3n vcc (net41 0) vsource dc=5 type=dc vdc_lo (net43 0) vsource dc=3.37 type=dc vdc_rf (net45 0) vsource dc=2.3 type=dc rl1 (net41 net55) resistor r=1K r46 (net43 net49) resistor r=60 r45 (net65 net51) resistor r=30 r44 (net65 0) resistor r=450 q56 (net55 net43 net64 0) NPNupper area=1 q57 (net41 net49 net64 0) NPNupper area=1 q58a (net64 net45 net65 0) NPNlower area=1 q58b (net64 net45 net65 0) NPNlower area=1 simulator lang=ads end rfExmplTrain_ne600_ADS_schematic #endif |
Title: Re: Complex Analog/RF/DSP IC design tool/flow Post by pancho_hideboo on Apr 14th, 2009, 5:55am currant wrote on Apr 14th, 2009, 3:55am:
currant wrote on Apr 14th, 2009, 1:55am:
After ADS2009U2, RFDE and Dynamic Link might be still available, but it can not be officially supported. |
Title: Re: Complex Analog/RF/DSP IC design tool/flow Post by currant on Apr 14th, 2009, 6:30am Yes, for this moment problem resolved. I worried about simulation with real PDK, but You already gave answer. Quote:
It's not good. It seems, that I need more accurately select set of tools. Now, I know litle bit more about Cadence RF Design Methodology Kit (there is Simulink co-simulation possible) - set of tools for this Kit is very expensive. Using GoldenGate + Ptolemy source/sink looks like not complete system simulation way (may be I wrong). I will reread Your posts. |
Title: Re: Complex Analog/RF/DSP IC design tool/flow Post by pancho_hideboo on Apr 14th, 2009, 6:52am currant wrote on Apr 14th, 2009, 6:30am:
With only Spectre licence, you can do cosimulation between Spectre and Simulink. I don't use cosimulation between Spectre and Simulink although I have Spectre and Simulink. Maybe if you use them, you could understand reason why I don't use it. currant wrote on Apr 14th, 2009, 6:30am:
"Source" is no more than Vector Signal Generator to generate Digital Modulation Signal. "Sink" is no more than Vector Signal Analyzer, BER Meter, Oscilloscope. Currently you can not simulate true mixed signal interaction using Ptolemy in GoldenGate. But if you write signal processing blocks using Verilog-D(SystemVerilog), you can do simulate true mixed signal interaction using NCsim in GoldenGate. So I don't think this is problem because we have to write RTL finally. |
Title: Re: Complex Analog/RF/DSP IC design tool/flow Post by currant on Apr 15th, 2009, 6:19am Hi, pancho_hideboo. I've read many times Your very usefull posts, not only in this branch and briefly looked through docs. So, now I think I undestand why You want to insert FastSPICE in design flow. In my system I wanted to use (under master DT simulator) in design/verification process as far as possible envelop analysis and avoid transient analysis. But as soon as designer of block introducies Verilog-A model I must avoid hidden states independent of frameworks (ADE, ADS,Simulink ....). And in most cases I must use transient analysis. In my chip BandPass sigma-delta ADC is a core. And the core of it is verilog-a function z-transform . So I must use only tran analys when I verify the model of ADC in my system. And so there is no difference what simulator (spectre, ADSSim, GoldeGate...) I am using. Is UltraSim - FastSPICE simulator? Quote:
After briefly reading userGuide of GoldenGate I don't undestand how we can use this sort of co-simulation? GoldenGate understand only Verilog-A. Many Thanks, pancho_hideboo. PS. Your post about AWR MWO is great help in question of tools for top-down mixed/analog/RF IC design. |
Title: Re: Complex Analog/RF/DSP IC design tool/flow Post by pancho_hideboo on Apr 15th, 2009, 6:56am currant wrote on Apr 15th, 2009, 6:19am:
As I said, you don't have to care about hidden state of models in both Ptolemy and Simulink. currant wrote on Apr 15th, 2009, 6:19am:
I want to introduce BDA's FastSpice in my design environment. http://www.berkeley-da.com/index.htm This transient simulator is most superior in current all commercial simulators. currant wrote on Apr 15th, 2009, 6:19am:
"Mixed Signal transient co-simulations of RF and Verilog-AMS" was introduced in GoldenGate-4.2. http://www.agilent.com/about/newsroom/presrel/2008/22apr-em08074.html http://www.home.agilent.com/agilent/product.jspx?cc=US&lc=eng&ckey=1374940&nid=-34269.804573.00&id=1374940 http://www.home.agilent.com/agilent/product.jspx?cc=US&lc=eng&ckey=1507014&nid=-34269.870794.00&id=1507014 http://edocs.soco.agilent.com/display/gg432/GoldenGate+RFIC+Simulator+Release+Notes http://www.designers-guide.org/Forum/YaBB.pl?num=1232855139 http://www.designers-guide.org/Forum/YaBB.pl?num=1232220194/5#5 Cosimulation using Envelope and Verilog-AMS will be introduced this summer. |
Title: Re: Complex Analog/RF/DSP IC design tool/flow Post by currant on Apr 16th, 2009, 2:17am Hi, pancho_hideboo. Sorry for my persistence. I am trying to achieve as more as possible clearness before I will start the work with simulators. pancho_hideboo wrote on Apr 15th, 2009, 6:56am:
As I undestood You meant internal models/blocks of Ptolemy and Simulink. Simulink doesn't simulate Verilog-A/AMS models, it only can export RF block as a Verilog-A description. Ptolemy can simulate Verilog-A models only via co-simulation with ADSSim tran and envelope analysis, so all troubles of hidden states still exist. Is't it? pancho_hideboo wrote on Mar 28th, 2009, 5:27am:
As I undestand the nature of this, is very similar to source/sink import to GoldenGate. Am I right? Can You give me a link to ADS documents, where it is describe how I must convert netlist from spectre in order to use it with ADSSim? Do You correct netlist by hand on? About BDA's FastSpice. It seems very good, can You provide me links for forum topics about about BDA's FastSpice? Is it understand spectre models? Is it easy build in ADE framework? pancho_hideboo wrote on Apr 15th, 2009, 6:56am:
So, will we not suffer from hidden states of couple of Verilog-A blocks and envelop analysis? Many thanks, pancho_hideboo. |
Title: Re: Complex Analog/RF/DSP IC design tool/flow Post by pancho_hideboo on Apr 16th, 2009, 3:23am currant wrote on Mar 28th, 2009, 6:56am:
currant wrote on Mar 28th, 2009, 7:32am:
MATLAB are different from Simulink. Both MATLAB and Simulink can't understand Verilog-A and can't treat Verilog-A. currant wrote on Apr 16th, 2009, 2:17am:
currant wrote on Apr 16th, 2009, 2:17am:
currant wrote on Apr 16th, 2009, 2:17am:
In cosimulation, Verilog-A models and Analog part of Verilog-AMS are treated by ADSsim not Ptolemy. Simulink models are treated by Simulink not by MMSIM(Spectre). Ptolemy models are treated by Ptolemy by neither MMSIM(Spectre) nor ADSsim. currant wrote on Apr 16th, 2009, 2:17am:
Again you don't have to care about hidden state of models in both Ptolemy and Simulink, because they are not treated by ADSsim or MMSIM(Spectre). currant wrote on Apr 16th, 2009, 2:17am:
currant wrote on Apr 16th, 2009, 2:17am:
currant wrote on Apr 16th, 2009, 2:17am:
currant wrote on Apr 16th, 2009, 2:17am:
Contact BDA's distributor or sales. http://www.berkeley-da.com/cont/index.htm currant wrote on Apr 16th, 2009, 2:17am:
But you don't have to care about hidden state of Verilog-D or Digital portions in Verilog-AMS because they are treated by NCsim not GoldenGate. In Mixed-signal systems, you need mixed analysis of following three domains. - CT(Continuous Time) ; Tran, Envelope simulator such as ADSsim, GoldenGate, MMSIM(Spectre), MMSIM in AMSD - DT(Discrete Time) ; SDF/TSDF simulator such as Ptolemy, Simulink, SPW(CoWare SPD), SystemVue, etc. - DE(Discrete Event or Event Driven) ; NCSim, VCS, ModelSim Domain or Analyis Engine where you have to care about hidden state is only CT(Continuous Time). Verilog-A or Analog portions in Verilog-AMS are treated by CT analysis engine. Verilog-D or Digital portions in Verilog-AMS are treated by DE analysis engine. Ptolemy models and Simulink models are treated by DT analysis engine. Models of SPW(CoWare SPD) can be also treated by DE analysis engine. I don't think your application aim for RF intensively. I don't think Ptolemy models are needed for your applications. Also I don't think you need Cadence NCsim for your applications. So you don't need Cadence AMSD. So for your purpose, I recommend you to use cosimulation between Cadence Spectre and Mathworks Simulink. If you already have Cadence Spectre and Mathworks Simulink, you can easily do cosimulation for your purpose. |
Title: Re: Complex Analog/RF/DSP IC design tool/flow Post by currant on Apr 16th, 2009, 4:46am pancho_hideboo wrote on Apr 16th, 2009, 3:23am:
This is my bad English, therefore there is a fragment from datasheet of RF toolbox: "RF Toolbox software lets you export a Verilog-A model of an rfmodel object. The toolbox provides one rfmodel object, rfmodel.rational, that you can use to represent any RF component or network for export to Verilog-A." pancho_hideboo wrote on Apr 16th, 2009, 3:23am:
I meant, Are here (in this forum), topics about BDA FastSPICE? pancho_hideboo wrote on Apr 16th, 2009, 3:23am:
I meant, how can/must I modify spectre netlist in order to use it with ADSSim. Is there automatic procedure, or I will need do it by hand. I will try it and after, if I have problem, ask about this. Your help was/is invaluable. |
Title: Re: Complex Analog/RF/DSP IC design tool/flow Post by pancho_hideboo on Apr 16th, 2009, 4:50am currant wrote on Apr 16th, 2009, 4:46am:
First, this is Toolbox of MATLAB not Blockset of Simulink. Second, this is not for cosimulation. This is just translation of mathematical equations for nonlinear input/output characteristics of MATLAB to Verilog-A. currant wrote on Apr 16th, 2009, 4:46am:
http://www.designers-guide.org/Forum/YaBB.pl?num=1183646486/11#11 currant wrote on Apr 16th, 2009, 4:46am:
currant wrote on Apr 16th, 2009, 4:46am:
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Title: Re: Complex Analog/RF/DSP IC design tool/flow Post by currant on Apr 16th, 2009, 5:11am pancho_hideboo wrote on Apr 16th, 2009, 4:50am:
Yes, I did some mistake, but in RF Blockset doc there is no "Verilog-A" word at all. Now, I clearly undestand: there is no Verilog-A cosimulation nor Simulink nether MATALB.) pancho_hideboo wrote on Apr 16th, 2009, 4:50am:
netlist. |
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