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Simulators >> RF Simulators >> is this a bug of cadence spectre? i'm hoping reply from Ken
https://designers-guide.org/forum/YaBB.pl?num=1239296124

Message started by mydreamhouse on Apr 9^th, 2009, 9:55am

Title: is this a bug of cadence spectre? i'm hoping reply from Ken
Post by mydreamhouse on Apr 9^th, 2009, 9:55am

now, i am simulating a receiver with cadence spectre, it is a typical heterodyne receiver, which including LNA, first Mixer, IF filter,second mixer, baseband filter,VGA and ADC. all the block are connected with packge model( no couple between pins) except the ADC and i make a TRAN analysis, the output of receiver is fine. but if i add the ADC clock and ADC block into top view ( there is no connection between ADC and the other circuit), a strange result appears, the RF signal is abnormal, which is disturbed by ADC clock. after my carefully checking, i found that if there is a steep transient block in circuit, such as VPULSE, whether it is connected with others ,the accuracy of the RF blocks is affected by the block. so the result is abnormal.
By the way, the accuracy of TRAN is moderate.
if i change it to conservative or set relref to allocal, the output is fine.
i'm hoping reply from Ken, thanks

Title: Re: is this a bug of cadence spectre? i'm hoping reply from Ken
Post by mydreamhouse on Apr 9^th, 2009, 10:07am

the abnormal signal is attached

Title: Re: is this a bug of cadence spectre? i'm hoping reply from Ken
Post by rf-design on Apr 10^th, 2009, 1:56am

If the VPULSE source is not connected and gives the disturbing result in a moderate accuracy setting it is the additional time step which is scheduled by the simulator. If the accuracy setting is moderate or the maximum time step is not set to low values the additional time step would change the integration error by the time pattern of the VPULSE source.

I know this effect for long time. It is a good decision to insert additional time steps at the discontinious points of the sources. Some years ago I had some discussions with DOLPHIN because they also schedule time steps in SMASH where VSIN crosses zero. That lead in high-Q circuit to similar disturbing behaviour. They fix this.

For discontinious sources it makes sense, for infinite differentiable signals not.

Please use progessive increase of accuracy until the result (waveform) does not change any more. Instead of moderate/liberal ... use your own accuracy setting (max time step, absolute, and relative accuracy) for spice.

Title: Re: is this a bug of cadence spectre? i'm hoping reply from Ken
Post by mydreamhouse on Apr 10^th, 2009, 10:46am

rf-design, thank your for your patience.
BTW, Cadence ultrasim has the same problem. i adjust the setting, and get a reasonable result, but the simulation speed down.
for a new design ,how to adjust setting ? it is a time consume and dummy work.(i just specify a setting, and wait the result and try others)

Title: Re: is this a bug of cadence spectre? i'm hoping reply from Ken
Post by pancho_hideboo on Apr 10^th, 2009, 9:46pm

mydreamhouse wrote on Apr 10^th, 2009, 10:46am:

BTW, Cadence ultrasim has the same problem. i adjust the setting, and get a reasonable result, but the simulation speed down.
for a new design ,how to adjust setting ?

See http://www.designers-guide.org/Forum/YaBB.pl?num=1237627988