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Simulators >> Circuit Simulators >> How to simulate this circuit in Spectre???
https://designers-guide.org/forum/YaBB.pl?num=1240322183
Message started by Yutao Liu on Apr 21st, 2009, 6:56am

Title: How to simulate this circuit in Spectre???
Post by Yutao Liu on Apr 21st, 2009, 6:56am
Hello everyone,

I want to observe gm of a nmos with a constant drain current but different vds.
The drain of nmos is connected with a current source and its source is connected to ground. How should I connect the gate of the nmos, when the drain current is constant but the vds is varying?

This circuit can be simulated in Hspice with a negative feedback, making use of amplifier, as descried in UC Berkeley EE240. However, the circuit can't work at Spectre due to problem of convergence.

Could anybody help?

Thanks!

Title: Re: How to simulate this circuit in Spectre???
Post by sheldon on Apr 21st, 2009, 7:41am
Yutao,

  The testbench setup is discussed in the append

http://www.cadence.com/Community/blogs/rf/archive/2008/08/09/simulating-mos-transistor-ft.aspx?postID=10665

The application is testing MOS transistor ft but the testbench can also
be used for the application you are describing.

                                                       Best Regards,

                                                          Sheldon

Title: Re: How to simulate this circuit in Spectre???
Post by Yutao Liu on Apr 22nd, 2009, 2:29am
Thank you, sheldon.

However, the picture in the website is not clear. could you send me a netlist of that testbench?

Thanks a lot!

Title: Re: How to simulate this circuit in Spectre???
Post by Yutao Liu on Apr 26th, 2009, 8:26pm

sheldon wrote on Apr 21st, 2009, 7:41am:
Yutao,

  The testbench setup is discussed in the append

http://www.cadence.com/Community/blogs/rf/archive/2008/08/09/simulating-mos-transistor-ft.aspx?postID=10665

The application is testing MOS transistor ft but the testbench can also
be used for the application you are describing.

                                                       Best Regards,

                                                          Sheldon


hi, Sheldon.
I have tried the testbench you recommended, however the result seems inconsistent with prediction. And I found that the drain current of the MOSFET did change when sweeping vds, which seems deviate my requirement obviously.Did you try that testbench? Why the drain current would change?

And I change the testbench a little (as shown below), and the result seems more reasonable. Is my testbench feasible to simulate what I want?
What's your opinion?
Thanks!

Title: Re: How to simulate this circuit in Spectre???
Post by pancho_hideboo on Apr 27th, 2009, 3:35am

Yutao Liu wrote on Apr 26th, 2009, 8:26pm:
And I change the testbench a little (as shown below), and the result seems more reasonable.
Is my testbench feasible to simulate what I want?
What on earth do you want to do ? :-/
How is your result reasonable ? :-*

Instance "G0" which is VCCS has no meaning at all because control voltage of "G0" is always zero.
And both "I0" and "V3" also have no meaning at all.
Your circuit is no more than NMOS FET where Source is ground, Drain is 1.0V and Gate is opened.

Previously you said "I'm a student for analog/RF circuit design". :D
http://www.designers-guide.org/Forum/YaBB.pl?num=1235705814/6#6

What on earth are you learning ?
Are you surely learning analog/RF circuit design ? :-?

What you want to do is setting Gate voltage automatically to give target value as Source current at Vds=constant ?
If so, remove "I0" and replace "G0" with combinations of ideal OP-Amp, CCVS controled by current flowing through "V3" and reference voltage.

I think test bench which sheldon showed also can work for this purpose.
Maybe CCCS is used in this test bench.
http://www.cadence.com/Community/blogs/rf/archive/2008/08/09/simulating-mos-transistor-ft.aspx?postID=10665
However I think current monitor should be inserted to drain(collector) not source(emitter).

Title: Re: How to simulate this circuit in Spectre???
Post by subgold on Apr 27th, 2009, 1:38pm

pancho_hideboo wrote on Apr 27th, 2009, 3:35am:

Yutao Liu wrote on Apr 26th, 2009, 8:26pm:
And I change the testbench a little (as shown below), and the result seems more reasonable.
Is my testbench feasible to simulate what I want?
What on earth do you want to do ? :-/
How is your result reasonable ? :-*

Instance "G0" which is VCCS has no meaning at all because control voltage of "G0" is always zero.
And both "I0" and "V3" also have no meaning at all.
Your circuit is no more than NMOS FET where Source is ground, Drain is 1.0V and Gate is opened.

Previously you said "I'm a student for analog/RF circuit design". :D
http://www.designers-guide.org/Forum/YaBB.pl?num=1235705814/6#6

What on earth are you learning ?
Are you surely learning analog/RF circuit design ? :-?

What you want to do is setting Gate voltage automatically to give target value as Source current at Vds=constant ?
If so, remove "I0" and replace "G0" with combinations of ideal OP-Amp, CCVS controled by current flowing through "V3" and reference voltage.

I think test bench which sheldon showed also can work for this purpose in case of MOSFET.
Maybe CCCS is used in this test bench.
http://www.cadence.com/Community/blogs/rf/archive/2008/08/09/simulating-mos-transistor-ft.aspx?postID=10665
However I think current monitor should be inserted to collector not emitter in case of BJT.


i think what yutao wants is not setting Gate voltage automatically to give target value as Source current at Vds=constant , but setting Vds to automatically give target Vgs at Ids=constant .

i think the straightforward way is to connect source to ground, drain to a constant idc, put the drain voltage and a ref voltage to the inputs of an ideal opamp, connect the opamp output to the gate.

Title: Re: How to simulate this circuit in Spectre???
Post by Yutao Liu on Apr 27th, 2009, 6:56pm

subgold wrote on Apr 27th, 2009, 1:38pm:

pancho_hideboo wrote on Apr 27th, 2009, 3:35am:

Yutao Liu wrote on Apr 26th, 2009, 8:26pm:
And I change the testbench a little (as shown below), and the result seems more reasonable.
Is my testbench feasible to simulate what I want?
What on earth do you want to do ? :-/
How is your result reasonable ? :-*

Instance "G0" which is VCCS has no meaning at all because control voltage of "G0" is always zero.
And both "I0" and "V3" also have no meaning at all.
Your circuit is no more than NMOS FET where Source is ground, Drain is 1.0V and Gate is opened.

Previously you said "I'm a student for analog/RF circuit design". :D
http://www.designers-guide.org/Forum/YaBB.pl?num=1235705814/6#6

What on earth are you learning ?
Are you surely learning analog/RF circuit design ? :-?

What you want to do is setting Gate voltage automatically to give target value as Source current at Vds=constant ?
If so, remove "I0" and replace "G0" with combinations of ideal OP-Amp, CCVS controled by current flowing through "V3" and reference voltage.

I think test bench which sheldon showed also can work for this purpose in case of MOSFET.
Maybe CCCS is used in this test bench.
http://www.cadence.com/Community/blogs/rf/archive/2008/08/09/simulating-mos-transistor-ft.aspx?postID=10665
However I think current monitor should be inserted to collector not emitter in case of BJT.


i think what yutao wants is not setting Gate voltage automatically to give target value as Source current at Vds=constant , but setting Vds to automatically give target Vgs at Ids=constant .

i think the straightforward way is to connect source to ground, drain to a constant idc, put the drain voltage and a ref voltage to the inputs of an ideal opamp, connect the opamp output to the gate.


Thanks for your reply!
I am really a student studying analog/RF design, although I am not so familiar with analog design as you.

What subgold said above is what i want to obtain.
I want to use gm/Id methodology to design my circuit. And according to the notes from EE240 UC berkeley, I have to choose a appropriate channel length of MOS for a given gain first. So, I want to know the intrinsic gain(gm*ro) of MOS with different channel length when sweeping vds under a constant Ids.
I had tried the method mentioned by subgold in Spectre for several times, and I used VCVS as the ideal opamp, with the gain of 100. However, the simulator warned that Vgs and Vds exceeded the breakdown voltage, and the simulation result shown below. Is the gain of the ideal opamp set too high? Or is there any mistakes I have made?

Title: Re: How to simulate this circuit in Spectre???
Post by pancho_hideboo on Apr 27th, 2009, 9:43pm

Yutao Liu wrote on Apr 27th, 2009, 6:56pm:
I am really a student studying analog/RF design, although I am not so familiar with analog design as you.
Study hard. ;D


Yutao Liu wrote on Apr 27th, 2009, 6:56pm:
I want to know the intrinsic gain(gm*ro) of MOS with different channel length when sweeping vds under a constant Ids.
Testbench which sheldon showed, my suggestion and subgold suggestion are all valid for your purpose.

You don't seem to understand DC characteristics of MOSFET.
Drain current of MOSFET, Ids is dependent on both Vgs and Vds. So Ids=Ids(Vgs, Vds).

What you want to do is setting gate bias Vgs automatically for swept Vds under keeping Ids as constant value.　

Testbench which sheldon showed is attractive because it doesn't require ideal-opamp.


Yutao Liu wrote on Apr 27th, 2009, 6:56pm:
I had tried the method mentioned by subgold in Spectre for several times, and I used VCVS as the ideal opamp.
Use "ahdllib/opamp with gain=100dB" instead of "analogLib/vcvs".

Title: Re: How to simulate this circuit in Spectre???
Post by subgold on Apr 28th, 2009, 3:01am

Yutao Liu wrote on Apr 27th, 2009, 6:56pm:

subgold wrote on Apr 27th, 2009, 1:38pm:

pancho_hideboo wrote on Apr 27th, 2009, 3:35am:

Yutao Liu wrote on Apr 26th, 2009, 8:26pm:
And I change the testbench a little (as shown below), and the result seems more reasonable.
Is my testbench feasible to simulate what I want?
What on earth do you want to do ? :-/
How is your result reasonable ? :-*

Instance "G0" which is VCCS has no meaning at all because control voltage of "G0" is always zero.
And both "I0" and "V3" also have no meaning at all.
Your circuit is no more than NMOS FET where Source is ground, Drain is 1.0V and Gate is opened.

Previously you said "I'm a student for analog/RF circuit design". :D
http://www.designers-guide.org/Forum/YaBB.pl?num=1235705814/6#6

What on earth are you learning ?
Are you surely learning analog/RF circuit design ? :-?

What you want to do is setting Gate voltage automatically to give target value as Source current at Vds=constant ?
If so, remove "I0" and replace "G0" with combinations of ideal OP-Amp, CCVS controled by current flowing through "V3" and reference voltage.

I think test bench which sheldon showed also can work for this purpose in case of MOSFET.
Maybe CCCS is used in this test bench.
http://www.cadence.com/Community/blogs/rf/archive/2008/08/09/simulating-mos-transistor-ft.aspx?postID=10665
However I think current monitor should be inserted to collector not emitter in case of BJT.


i think what yutao wants is not setting Gate voltage automatically to give target value as Source current at Vds=constant , but setting Vds to automatically give target Vgs at Ids=constant .

i think the straightforward way is to connect source to ground, drain to a constant idc, put the drain voltage and a ref voltage to the inputs of an ideal opamp, connect the opamp output to the gate.


Thanks for your reply!
I am really a student studying analog/RF design, although I am not so familiar with analog design as you.

What subgold said above is what i want to obtain.
I want to use gm/Id methodology to design my circuit. And according to the notes from EE240 UC berkeley, I have to choose a appropriate channel length of MOS for a given gain first. So, I want to know the intrinsic gain(gm*ro) of MOS with different channel length when sweeping vds under a constant Ids.
I had tried the method mentioned by subgold in Spectre for several times, and I used VCVS as the ideal opamp, with the gain of 100. However, the simulator warned that Vgs and Vds exceeded the breakdown voltage, and the simulation result shown below. Is the gain of the ideal opamp set too high? Or is there any mistakes I have made?


somehow i didn't notice sheldon's post at the first place, now i see it, and i agree with pancho_hideboo that it is quite simple and nice. you may also try that out.

anyway, i dont see why the bench using opamp feedback fails. 100 gain is not high at all (or did you mean 100db?) please post ur schematic and result waveforms (not only the gm curve you posted) so that others can check if there is any mistake.

Title: Re: How to simulate this circuit in Spectre???
Post by Yutao Liu on Apr 28th, 2009, 7:08am

subgold wrote on Apr 28th, 2009, 3:01am:
somehow i didn't notice sheldon's post at the first place, now i see it, and i agree with pancho_hideboo that it is quite simple and nice. you may also try that out.


Hi, subgold and  pancho_hideboo, thanks for your suggestion and patient.
Both of you really have taught me a lot.

I tried the testbench Sheldon introduced, both schematic and result waveforms are shown below.  I am sure that the schematic is totally the same as that in
http://www.cadence.com/Community/blogs/rf/archive/2008/07/16/measuring-transistor-ft.aspx?postID=10226
And I do the DC analysis with sweeping vds from 0 to 3.2 V, plotting the operation points as shown below.

However, I doubt the result because the drain current linearly increase in the range between 0 and 800pA, while I want the drain current keeps constant. Did I do something wrong during simulating?

Thank you so much!!!
Best regards!
Yutao

Title: Re: How to simulate this circuit in Spectre???
Post by pancho_hideboo on Apr 28th, 2009, 8:10am

Yutao Liu wrote on Apr 28th, 2009, 7:08am:
And I do the DC analysis with sweeping vds from 0 to 3.2 V, plotting the operation points as shown below.
Show me your netlists with model file of "n18".

Show me Id-Vds characteristics of "n18" with L and W of your setting for various Vgs.
For example,
Vgs ; start=0.0, stop=0.8, step=0.1
Vds ; start=0.0, stop=3.2, step=0.01

Title: Re: How to simulate this circuit in Spectre???
Post by Yutao Liu on Apr 28th, 2009, 7:25pm

pancho_hideboo wrote on Apr 28th, 2009, 8:10am:

Yutao Liu wrote on Apr 28th, 2009, 7:08am:
And I do the DC analysis with sweeping vds from 0 to 3.2 V, plotting the operation points as shown below.
Show me your netlists with model file of "n18".

Show me Id-Vds characteristics of "n18" with L and W of your setting for various Vgs.
For example,
Vgs ; start=0.0, stop=0.8, step=0.1
Vds ; start=0.0, stop=3.2, step=0.01

hi pancho_hideboo, following is the id-Vds characteristics of "n18".

Title: Re: How to simulate this circuit in Spectre???
Post by pancho_hideboo on Apr 28th, 2009, 7:52pm

Yutao Liu wrote on Apr 28th, 2009, 7:25pm:
following is the id-Vds characteristics of "n18".
I think it is impossible to get Ids=200uA with "n18" of your L and W.
Increase W.

Show me your netlists with model file of "n18".

Title: Re: How to simulate this circuit in Spectre???
Post by Yutao Liu on Apr 28th, 2009, 8:24pm

pancho_hideboo wrote on Apr 28th, 2009, 7:52pm:

Yutao Liu wrote on Apr 28th, 2009, 7:25pm:
following is the id-Vds characteristics of "n18".
I think it is impossible to get Ids=200uA with "n18" of your L and W.
Increase W.

Show me your netlists with model file of "n18".

thank you so much, pancho_hideboo!
I also tried Ids=40uA and increase the W, but the Ids current still increases linearly.
attach is the netlists and the model of n18.
Thanks for your help again.

Title: Re: How to simulate this circuit in Spectre???
Post by pancho_hideboo on Apr 28th, 2009, 9:09pm

Yutao Liu wrote on Apr 28th, 2009, 8:24pm:
attach is the netlists and the model of n18.
Both statements of parameter definition and statements of analysis don't exist. >:(

As I said to you repeatedly, no one except for you knows your specific situations.
What sizes on earth did you use as W and L for "n18" ? >:(

Show me complete netlists. e.g. "input.scs" if you use Cadence Spectre from ADE.

Title: Re: How to simulate this circuit in Spectre???
Post by Yutao Liu on Apr 29th, 2009, 1:10am

pancho_hideboo wrote on Apr 28th, 2009, 9:09pm:

Yutao Liu wrote on Apr 28th, 2009, 8:24pm:
attach is the netlists and the model of n18.
Both statements of parameter definition and statements of analysis don't exist. >:(

As I said to you repeatedly, no one except for you knows your specific situations.
What sizes on earth did you use as W and L for "n18" ? >:(

Show me complete netlists. e.g. "input.scs" if you use Cadence Spectre from ADE.


I am sorry for my mistake.  :-[

input.rar is the input.scs file for my simulation.

And "op2 .scs" file listed inside is used to store the operating points while sweeping vds.
There is only one statement in "op2.scs", which is "save NM1:oppoint".

I hope information attached this time would be complete.

best regards

Title: Re: How to simulate this circuit in Spectre???
Post by subgold on Apr 29th, 2009, 1:30am

Yutao Liu wrote on Apr 29th, 2009, 12:33am:

pancho_hideboo wrote on Apr 28th, 2009, 9:09pm:

Yutao Liu wrote on Apr 28th, 2009, 8:24pm:
attach is the netlists and the model of n18.
Both statements of parameter definition and statements of analysis don't exist. >:(

As I said to you repeatedly, no one except for you knows your specific situations.
What sizes on earth did you use as W and L for "n18" ? >:(

Show me complete netlists. e.g. "input.scs" if you use Cadence Spectre from ADE.


I am sorry for my mistake.

input.rar is the input.scs file for my simulation.

And "op2 .scs" file listed inside is used to store the operating points while sweeping vds.
There is only one statement in "op2.scs", which is "save NM1:oppoint".

I hope information attached this time would be complete.

best regards


first thing to try, do not define w and l as variable. specify them directly in the transistor property in the schematic.

Title: Re: How to simulate this circuit in Spectre???
Post by pancho_hideboo on Apr 29th, 2009, 1:38am

Yutao Liu wrote on Apr 29th, 2009, 1:10am:
I hope information attached this time would be complete.
Still there are some unknown parameters like followings.
Are they all zero ?


Quote:
run Yutao_Liu.scs
.
Yutao_Liu.log

Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator
Version 6.2.0.493 -- 19 Sep 2007
Copyright (C) 1989-2007 Cadence Design Systems, Inc. All rights reserved
       worldwide. Cadence, Virtuoso and Spectre are registered trademarks of
       Cadence Design Systems, Inc. All others are the property of their
       respective holders.

Protected by U.S. Patents: 5,610,847; 5,790,436; 5,812,431; 5,859,785;
       5,949,992; 5,987,238; 6,088,523; 6,101,323; 6,151,698; 6,181,754;
       6,260,176; 6,278,964; 6,349,272; 6,374,390; 6,493,849; 6,504,885;
       6,618,837; 6,636,839; 6,778,025; 6,832,358; 6,851,097; 6,928,626;
       7,024,652; 7,035,782; 7,085,700; 7,143,021.

Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA
       Security, Inc.

Simulating `Yutao_Liu.scs' on lkenpc06 at 5:32:25 PM, Wed Apr 29, 2009.

Error found by spectre during hierarchy flattening.
   ERROR (SFE-1999): "./n18.scs" 3: model `n18': parameter `tox': Unknown
       parameter name `dtox_n18' found in expression.
       
   ERROR (SFE-1999): "./n18.scs" 3: model `n18': parameter `xl': Unknown
       parameter name `dxl_n18' found in expression.
       
   ERROR (SFE-1999): "./n18.scs" 3: model `n18': parameter `xw': Unknown
       parameter name `dxw_n18' found in expression.
       
   ERROR (SFE-1999): "./n18.scs" 3: model `n18': parameter `vth0': Unknown
       parameter name `dvth_n18' found in expression.
       
   ERROR (SFE-1999): "./n18.scs" 3: model `n18': parameter `pvth0': Unknown
       parameter name `dpvth0_n18' found in expression.
       
spectre terminated prematurely due to fatal error.

Title: Re: How to simulate this circuit in Spectre???
Post by Yutao Liu on Apr 29th, 2009, 1:53am

subgold wrote on Apr 29th, 2009, 1:30am:

Yutao Liu wrote on Apr 29th, 2009, 12:33am:

pancho_hideboo wrote on Apr 28th, 2009, 9:09pm:

Yutao Liu wrote on Apr 28th, 2009, 8:24pm:
attach is the netlists and the model of n18.
Both statements of parameter definition and statements of analysis don't exist. >:(

As I said to you repeatedly, no one except for you knows your specific situations.
What sizes on earth did you use as W and L for "n18" ? >:(

Show me complete netlists. e.g. "input.scs" if you use Cadence Spectre from ADE.


I am sorry for my mistake.

input.rar is the input.scs file for my simulation.

And "op2 .scs" file listed inside is used to store the operating points while sweeping vds.
There is only one statement in "op2.scs", which is "save NM1:oppoint".

I hope information attached this time would be complete.

best regards


first thing to try, do not define w and l as variable. specify them directly in the transistor property in the schematic.


Thanks for subgold's suggestion.
I did this change before I change the w and l as variable. But the result did not change.
And when I run the simulation, the simulator warned me that  "Vgs has exceeded the oxide breakdown voltage"
Dose this warning matter? If so, how should I change my simulation?

Title: Re: How to simulate this circuit in Spectre???
Post by Yutao Liu on Apr 29th, 2009, 2:07am

pancho_hideboo wrote on Apr 29th, 2009, 1:38am:

Yutao Liu wrote on Apr 29th, 2009, 1:10am:
I hope information attached this time would be complete.
Still there are some unknown parameters like followings.
Are they all zero ?


Quote:
run Yutao_Liu.scs
.
Yutao_Liu.log

Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator
Version 6.2.0.493 -- 19 Sep 2007
Copyright (C) 1989-2007 Cadence Design Systems, Inc. All rights reserved
       worldwide. Cadence, Virtuoso and Spectre are registered trademarks of
       Cadence Design Systems, Inc. All others are the property of their
       respective holders.

Protected by U.S. Patents: 5,610,847; 5,790,436; 5,812,431; 5,859,785;
       5,949,992; 5,987,238; 6,088,523; 6,101,323; 6,151,698; 6,181,754;
       6,260,176; 6,278,964; 6,349,272; 6,374,390; 6,493,849; 6,504,885;
       6,618,837; 6,636,839; 6,778,025; 6,832,358; 6,851,097; 6,928,626;
       7,024,652; 7,035,782; 7,085,700; 7,143,021.

Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA
       Security, Inc.

Simulating `Yutao_Liu.scs' on lkenpc06 at 5:32:25 PM, Wed Apr 29, 2009.

Error found by spectre during hierarchy flattening.
   ERROR (SFE-1999): "./n18.scs" 3: model `n18': parameter `tox': Unknown
       parameter name `dtox_n18' found in expression.
       
   ERROR (SFE-1999): "./n18.scs" 3: model `n18': parameter `xl': Unknown
       parameter name `dxl_n18' found in expression.
       
   ERROR (SFE-1999): "./n18.scs" 3: model `n18': parameter `xw': Unknown
       parameter name `dxw_n18' found in expression.
       
   ERROR (SFE-1999): "./n18.scs" 3: model `n18': parameter `vth0': Unknown
       parameter name `dvth_n18' found in expression.
       
   ERROR (SFE-1999): "./n18.scs" 3: model `n18': parameter `pvth0': Unknown
       parameter name `dpvth0_n18' found in expression.
       
spectre terminated prematurely due to fatal error.

Oh, god! i forget to show you those datum again! Please forgive me!
Yes, those datum are all zero.
Please try this model file (attached) where all those datum have been set zero.

Thanks a lot.

Title: Re: How to simulate this circuit in Spectre???
Post by pancho_hideboo on Apr 29th, 2009, 4:31am
Attached is a method I suggested in http://www.designers-guide.org/Forum/YaBB.pl?num=1240322183/4#4
Your NMOS FET is connected to nodes, "d", "g", "s" and "GND".

From practical point of view, a method subgold suggested is more good because input signals of OPAmp is very small in my method.

Indeed I don't use any of the followings.
  - Testbench which sheldon showed
  - my suggestion
  - subgold suggestion

I use Agilent ADSsim(RFDE) for device characterizations.
Here I invoke optimizer with parametric sweep.

[Parametric Sweep of vds]
    [Optimization of vgs for target Ids under vds]
      [Final Analysis such as DCOP, SP, AC, Noise under seached bias conditions, vgs, vds, Ids]

The followings are non parametric sweep case.
http://www.designers-guide.org/Forum/YaBB.pl?num=1212376329/3#3
http://www.designers-guide.org/Forum/YaBB.pl?num=1203057659/7#7

As you said to us, testbench which sheldon showed don't seem to work correctly.
Later I will investigate causes.

Title: Re: How to simulate this circuit in Spectre???
Post by subgold on Apr 29th, 2009, 6:36am

Yutao Liu wrote on Apr 29th, 2009, 1:53am:

subgold wrote on Apr 29th, 2009, 1:30am:

Yutao Liu wrote on Apr 29th, 2009, 12:33am:

pancho_hideboo wrote on Apr 28th, 2009, 9:09pm:

Yutao Liu wrote on Apr 28th, 2009, 8:24pm:
attach is the netlists and the model of n18.
Both statements of parameter definition and statements of analysis don't exist. >:(

As I said to you repeatedly, no one except for you knows your specific situations.
What sizes on earth did you use as W and L for "n18" ? >:(

Show me complete netlists. e.g. "input.scs" if you use Cadence Spectre from ADE.


I am sorry for my mistake.

input.rar is the input.scs file for my simulation.

And "op2 .scs" file listed inside is used to store the operating points while sweeping vds.
There is only one statement in "op2.scs", which is "save NM1:oppoint".

I hope information attached this time would be complete.

best regards


first thing to try, do not define w and l as variable. specify them directly in the transistor property in the schematic.


Thanks for subgold's suggestion.
I did this change before I change the w and l as variable. But the result did not change.
And when I run the simulation, the simulator warned me that  "Vgs has exceeded the oxide breakdown voltage"
Dose this warning matter? If so, how should I change my simulation?


i think the warning is exactly the problem. since your netlist looks fine, i think it is purely a simulator related problem, because everyting is ideal here, the cccs is also modeled as an ideal current source, which has very high impedance (seems to be 10^12ohm). therefore, with the current of the ideal current source, your gate voltage goes crazy and the correct dc operation points are never obtained.

try to clamp a diode there, with anode connected to the gate, and cathode connected to the max. allowed voltage (vdd), and see if it works.

Title: Re: How to simulate this circuit in Spectre???
Post by pancho_hideboo on Apr 29th, 2009, 9:19pm
This is a method which subgold suggested. Here I used Cadence Spectre.

Title: Re: How to simulate this circuit in Spectre???
Post by pancho_hideboo on Apr 29th, 2009, 10:07pm
This is a result of Agilent ADSsim.

Title: Re: How to simulate this circuit in Spectre???
Post by Yutao Liu on Apr 30th, 2009, 1:46am

pancho_hideboo wrote on Apr 29th, 2009, 9:19pm:
This is a method which subgold suggested. Here I used Cadence Spectre.


Thanks for pancho_hideboo's reply.
The simulation results exactly meet what i want.

But I don't quite understand why the opamp in ahdlLib is able to achieve the result while the vcvs in analogLib fails, since both of them are used to make the drain voltage keep tracked with "Vds" while sweeping, and to stabilize the gate voltage?
What 's the difference between them?

Best regards!

Title: Re: How to simulate this circuit in Spectre???
Post by sheldon on Apr 30th, 2009, 5:31am
Yutao,

  If you want measure gm, why don't you limit the sweep range
to bias conditions where the device is in saturation? You are forcing
the Vds to be perfectly 0, vds=0, at the same time you are forcing
the transistor to conduct a finite current, ibias=40u. This condition
is not physical so the model and the testbench react non-physically.  
If you sweep the Vds from 3.2V to 0V, you will see that the Vgs
becomes large as the Vds approaches 0 and that the curve starts
to break up at about Vd,sat. The op-amp model clamps at the supply
voltage so that  the results look better. Also you will need to use
a different testbench to measure rds when Vds < Vds,sat.

                                                        Best Regards,

                                                           Sheldon  

Title: Re: How to simulate this circuit in Spectre???
Post by pancho_hideboo on May 1st, 2009, 4:51am
A method which subgold suggested is unreasonable for low Vds region.
A method which my suggested is more reasonable for low Vds region.

Indeed I don't use any of the followings.
 - Testbench which sheldon showed
 - my suggestion
 - subgold suggestion

I use Agilent ADSsim(RFDE) for device characterizations.
Here I invoke optimizer with parametric sweep.

Attached figure is an example I'm using for device characterization, here I use SP-Analysis as FinalAnalysis of Optimizer.

[Parametric Sweep of Idrain ; Sweep2]
  [Parametric Sweep of Vds ; Sweep1]
       [Optimization of Vgs for target Idrain under Vds ; Optim1 with DC1]
     [SP Analysis as Final Analysis under seached bias conditions, Vgs, Vds, Idrain ; SP1]

This result is also reasonable for low Vds region.

Title: Re: How to simulate this circuit in Spectre???
Post by sheldon on May 1st, 2009, 6:12am
Yutao,

  I am curious about your original testbench. I was looking at the
EE240 website lecture on MOS transistors and found the references
on these pages. Was this your original testbench the circuit described
on page 14?

https://www.eecs.berkeley.edu/~boser/courses/240_2004_sp/index.html

                                                                 Best Regards,

                                                                    Sheldon

Title: Re: How to simulate this circuit in Spectre???
Post by Yutao Liu on May 1st, 2009, 6:47am

sheldon wrote on May 1st, 2009, 6:12am:
Yutao,

  I am curious about your original testbench. I was looking at the
EE240 website lecture on MOS transistors and found the references
on these pages. Was this your original testbench the circuit described
on page 14?

https://www.eecs.berkeley.edu/~boser/courses/240_2004_sp/index.html

                                                                 Best Regards,

                                                                    Sheldon


Sheldon,
Not on page 14, but on page 33 instead.  And my reference is http://bwrc.eecs.berkeley.edu/classes/icdesign/ee240_s09/lectures/Lecture04_MOS_Small_Sig_2up.pdf on page 10.

I used the vcvs as the feedback opamp in spectre, and I failed.
I think the testbench that pancho_hideboo provided is feasible and the result looks the same as that on the notes.
But I still don't understand what difference between opamp in ahdlLib and vcvs in analogLib makes the simulation result different, even if I read your reply. Could you explain more clearly, please?
                                                                Best regards,
                                                                     Yutao

Title: Re: How to simulate this circuit in Spectre???
Post by Yutao Liu on May 1st, 2009, 7:05am

pancho_hideboo wrote on Apr 29th, 2009, 9:19pm:
This is a method which subgold suggested. Here I used Cadence Spectre.


Pancho_hideboo,
thanks for your work. I think your testbench is feasible and the result looks reliable.
I have tried your testbench in spectre, the result looks the same as yours basically, but discontinuity exist when vds is in low region, as shown below. My schematic and the setting of the opamp is totally the same as you described above. Do you have any idea what makes the discontinuity?
Thanks.

Best regards

yutao

Title: Re: How to simulate this circuit in Spectre???
Post by pancho_hideboo on May 1st, 2009, 8:14am

Yutao Liu wrote on Apr 30th, 2009, 1:46am:
The simulation results exactly meet what i want.
I don't think so.

Apparently you were trying to flow Idrain=200uA without confirming Id-Vds characteristics of "n18" with L=0.35um and W=1.0um.
It is very common rule to confirm Id-Vds characteristics of DUT before forced biasing.
Warning you saw, "Vgs has exceeded the oxide breakdown voltage" was quite natural result of your thoughtlessness.

If your trial was actual measurements, MOSFET might be broken.
Learn measurements using actual instruments. Not "EDA Tool Play".

A method which subgold suggested is unreasonable for low Vds region.
Compare results of (1) with results of (2) and (3).
 (1) subgold suggestion(Id is forced, Vds is monitored)
 (2) my suggestion(Vds is forced, Id is monitored)
 (3) Bias condition searching using Optimizer of Agilent ADSsim(Vds is forced, Id is monitored)


Yutao Liu wrote on Apr 30th, 2009, 1:46am:
But I don't quite understand why the opamp in ahdlLib is able to achieve the result while the vcvs in analogLib fails.
What 's the difference between them?
Maybe this is due to difference of behavior around in_p-in_n=0 between "analogLib/vcvs" and "ahdlLib/opamp".


Yutao Liu wrote on May 1st, 2009, 7:05am:
but discontinuity exist when vds is in low region, as shown below.
My schematic and the setting of the opamp is totally the same as you described above.
Do you have any idea what makes the discontinuity?
If you consider Id-Vds characteristics of "n18" with L=0.35um and W=1.0um,
this result is quite natural in condition of "Id is forced, Vds is monitored".

Title: Re: How to simulate this circuit in Spectre???
Post by sheldon on May 1st, 2009, 8:55am
Yutao,

  If you look at the testbenches the sweep is 0.2V to 3.5V. Again,
you can not force a constant current through a transistor when
Vds=0. Also the block in the Berkeley testbench is the diffamp
from ahdlLib, set the gain=100 as shown in the attachment.

                                                    Hope this helps,

                                                       Sheldon

Title: Re: How to simulate this circuit in Spectre???
Post by sheldon on May 1st, 2009, 8:56am
oops, the testbench

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