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Message started by gaom9 on Apr 23rd, 2009, 8:01am

Title: About the Standard Cell application in P&R
Post by gaom9 on Apr 23rd, 2009, 8:01am

Hi,
I am new in Digital circuit synthesis and P&R, so I have some questions about the Standard cell application in P&R.
I finish the synthesis in DC and use the SOC encounter to do the Place and Route, but when I import the GDS2 or DEF files which output from SOC encounter to Virtuoso, there are some errors, the layout view can not display right as shown in figure 1

Only the metal 1 and metal 2 can be displayed, the Standard Cell can not be displayed. Before I import the DEF file, I have added the Symbol lib of the Standard Cell lib and imported the LEF file to the CIW. But when I open the Standard Cell layout, it is not right as shown in figure 2


Is there anything I should pay attention to when import the LEF file? I thing is there any error in the layout map, I do not use the layout map file when import these file?
Also, I can not import the Verilog, after I import the Verilog, there are only ports in the schematic, but not the symbol.
Can anyone give me some advice, please?

Thank you!
Best regards!

Title: Re: About the Standard Cell application in P&R
Post by Andrew Beckett on Apr 24th, 2009, 6:55am

The LEF will typically only contain the abstracts of the cells, not the full layout - which is why you see what you see when you open the standard cell (I expect). You probably need to import the stream file (GDS) of the standard cell to get the full layout.

When you do the import of the GDS from Encounter (or the DEF), you probably need to specify your standard cell library as a reference library. It's not really clear what you've tried to do.

And it's not obvious what you did with importing the Verilog - were there errors, what did you try, etc etc?

Regards,

Andrew.

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