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Other CAD Tools >> Entry Tools >> Importing Verilog using Verilog In
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Message started by jefkat on Apr 29^th, 2009, 8:52am

Title: Importing Verilog using Verilog In
Post by jefkat on Apr 29^th, 2009, 8:52am

Hi,
I imported a big hierarchical verilog design into cadence using 'Verilog In' from CIW. The problem is that the generated functional views dont have include statements. As a result my
ams simulator compains about the defines that were being
referenced.
Any help?
shaf