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Message started by ic_engr on May 4th, 2009, 10:51am

Title: Doubler Sided CMOS substrate/wafer
Post by ic_engr on May 4th, 2009, 10:51am


I was wondering if anyone has come across a foundry that can perform lithography on both sides of the substrate. This would be interesting as one can double the capacity (# of gates) by having the design on both sides of the wafer without needing to move to finer technologies.

Any leads on this ???


Title: Re: Doubler Sided CMOS substrate/wafer
Post by vivkr on May 28th, 2009, 12:22am

I don't remember all the details but I think there was a presentation of some such device from ST at one conference. I think they called it FinFET and it has gates on both sides, above and below. What I don't remember is how they made the second gate. You might want to check it out.

By the way, you may double the number of wafers on both sides but you will also increase the processing costs enormously, atleast by factor 2x and probably more if you could do lithography on both sides. And you would need to punch vias through the wafer which is usually around 700 um thick to connect both sides. Plus packaging the die would be a big headache. You would need to atleast have all bond pads on one side of the die, and there would be possibly other issues such as mechanical and thermal robustness.

Nonetheless, I don't think it is impossible. The question is probably if it is useful or if equal amount of benefits cannot be realized by other, cheaper means.



Title: Re: Doubler Sided CMOS substrate/wafer
Post by RobG on Jun 3rd, 2009, 4:30pm

I think finFet is a different animal (check wiki The American Semiconductor FlexFet ( has a gate on top bottom, but it is really more of a bulk that is treated like a gate. THey use it to control Vt and claim to have a 0.5V process.

I don't think processing on top/bottom is done -- perhaps the via issue is the killer. On the other hand, you can stack chips on top of eachother and downbond from the top to the bottom. TI does some of this.

Title: Re: Doubler Sided CMOS substrate/wafer
Post by Berti on Jun 4th, 2009, 8:13am

Vivek, I agree with Rob. I think what you describe is an double-gate transistor. I am also sure that ST is doing research on that as double-gate transistors (better control of channel) are seen as the solution to smaller feature sizes.

Title: Re: Doubler Sided CMOS substrate/wafer
Post by vivkr on Jun 5th, 2009, 3:49am

My mistake. I mixed it up with another presentation. The device in question was called the "independently driven double-gate MOS" (IDGMOS) and has metal gates above and below the channel. It was developed by different groups, CEA-LETI & MINATEC in Grenoble and another one at the U. Bordeaux. Although ST is not mentioned in the author's list, we were told by one of the authors that it was basically their partner in this development and planning to use this.

The complete citation to the paper (presented at IEEE PRIME '07):

Analog Circuit Design Based on Independently Driven
Double Gate MOSfet
P.Freitas, G.Billiot
Grenoble, France
J.B. Begueret, H.Lapuyade
IMS IXL Laboratory
Talence, France



Title: Re: Doubler Sided CMOS substrate/wafer
Post by Colbhaidh on Jul 21st, 2009, 3:48am

Patterning on the back of wafers is quite common for through wafer VIAS that are used to stack chips on top of one another. Using the backside for actual circuitry would be difficult as many wafer handling systems use a vacuum chuck that would crush the layers beneath the susceptor. Also, the backsides of the wafer are often doped differently from the front side for defect gettering purposes.

Title: Re: Doubler Sided CMOS substrate/wafer
Post by RobG on Jul 27th, 2009, 7:27am

Thank you! Always good to learn something new.

Title: Re: Doubler Sided CMOS substrate/wafer
Post by loose-electron on Sep 6th, 2009, 10:16am

to the best of my knowledge putting transistors on both side of the wafer is not done for a number of reason -

Interactive lithography - the litho steps that include thermal cycles would affect both sides of the wafer, making for some interesting foundry process definitions.

Defect density - Now you got to get both sides to work and if one side is dead, then you toss the whole things.

Physical preparation - The cleaning, planarizing and polishing to prep wafer side needs a physical mount to do. Until the final passivation layer gets put on a wafer (hard and very tough to scratch) the lower levels can have some soft and easily damage pieces (think soft copper or older metal aluminum interconnects)

Connections thru the wafer in the form of interconnect vias has been done, but I am not sure how much it gets used right now.

Stacked chips are a pretty common thing right now in SIP (system in package) things.

Fin-FETS and other 3D transistors have been around for a while now in R&D but these are built up on one side of the wafer. Also multi layer structures with transistors stacked on top of each other have also been an R&D thing for a while but have not generated too much commercial interest, because the fabrication process is messy and expensive.

State of the art CMOS is at 13 atoms channel length and 4 atoms gate oxide thickness. Classic CMOS geometry scaling is coming to an end. (But havent we been saying that for the last 10 years?)

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