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Design >> High-Speed I/O Design >> L0S (EI) detector in Serial Links such as PCIE
https://designers-guide.org/forum/YaBB.pl?num=1241840487

Message started by neoflash on May 8^th, 2009, 8:41pm

Title: L0S (EI) detector in Serial Links such as PCIE
Post by neoflash on May 8^th, 2009, 8:41pm

Signal detection level of serial transceivers is from 65mV-ppd to 175mV-ppd, with 120mV-ppd as nominal detection threshold. (PCIE Gen2)

However, if the data pattern is clock and if there is 20dB attenuation
at baud rate, the signal amplitude will be close to 1/10 of
transmitter side full amplitude.

Assuming Tx amplitude is 1200mV-ppd, the rx side amplitude is 1/10 and close to 120mV-ppd. This signal will be rejected by input signal
detector and chip will enter electrical idle.

How we handle this?