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Simulators >> RF Simulators >> pss analysis of PLL
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Message started by jas on May 13^th, 2009, 11:54am

Title: pss analysis of PLL
Post by jas on May 13^th, 2009, 11:54am

Hello
I was performing in Cadence (ver. 5.10.41_USR2.19) the pss simulation but some problems occured.
Let me describe my system.
I'm making PLL which consists:
Reference voltage (square wave-vpulse): 4MHz
PFD/CP: 3 state, transitor level
Loop Filter: second order (R+C) || C
VCO (sinusoid): 300 MHz (Verilog-A example from Cadence 'pllLib')
Block to change vco sin to square and sent it to Divider.
Divider: N=79 (Verilog-A example from "Hidden State in SpectreRF" by
Ken Kundert)

(I have also transistor level divider and VCO which are working but
first I wanted to make pnoise simulation with these two ideal Verilog-
A models to save the time)

So, the transient simulation shown that PLL locks and the the
stabilization time is 10us.
Then I set the following parameters of PSS and Pnoise analysyis:
PSS:
Beat frequency: 4MHz (like desired frequency od out signal of divider)
Nr of harmonics: 79
Accuracy Defaults: moderate
Additional time for stabilization: 10us
(rest of parameters is default. The 'Oscillator' option is not checked)

Ok, when I run the pss simulation it was working until 10us. Then I noticed the convNorm was quite big like 27.2e+03 and the analysis was making loops. Nothing more happend so I had too stop the simulation.

So there is a problem with convergence. But in transient analysis the ripples of VCO control voltage, after 10us, were like 1mV which means 100kHz variation of VCO frequency (Kvco=100MHz/V). So there shouldn't be any problem.

So my question is:
Are the pss settings correct?

Thanks in advance for replies.

Title: Re: pss analysis of PLL
Post by Shahriar on Sep 11^th, 2010, 5:29pm

Have you found any solution to your problem? I'm facing the same problem.

Title: Re: pss analysis of PLL
Post by Ken Kundert on Sep 12^th, 2010, 8:36am

You're settings look okay to me at first glance. If the circuit is not converging it is generally because the circuit is either not close enough to periodic steady-state when the tstab interval ends, or the circuit simply does not have a periodic steady-state solution. To test these, rerun the circuit in transient analysis with strobing turned on and the strobe interval set exactly equal to the period of the fundamental frequency (generally the input frequency). Then examine all the waveforms in the circuit. Every signal should be close to its equilibrium value and there should be no ripple. If the signals are not close to their equilibrium points, set tstab to a larger value. If there is ripple of any kind, then either you have the wrong the fundamental frequency or your circuit does not have a periodic steady-state solution. If the circuit does not have a periodic steady-state solution, you cannot use RF analyses (shooting methods or harmonic balance). This generally occurs when the circuit is unstable (has a parasitic oscillation). Once you determine a time when the signals reach their equilibrium values, use this time as tstab in the PSS analysis. Once you determine a fundamental frequency that results in no ripple, use this as the "beat frequency" for the PSS analysis.

-Ken

Title: Re: pss analysis of PLL
Post by ssahl on Dec 30^th, 2010, 12:27pm

Hi,

are you sure the PLL has settled in 10us. The reference is 4MHz <=> 0.25us giving only 40 periods for recharging the loop filter.

If you have a zero in the loop filter if can takes very long time to recharge all capacitors in the filter to their final value. During that time the frequency i correct but there is a small phase error that slowly is integrated away. The ripple is low during this time.

Just an idea...