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Simulators >> RF Simulators >> Cadence Noise-Aware PLL Design Flow
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Message started by jenand on Jun 7^th, 2009, 5:34am

Title: Cadence Noise-Aware PLL Design Flow
Post by jenand on Jun 7^th, 2009, 5:34am

Hello,
I am using the Cadence Noise-Aware PLL Design flow to speed up the simulation of my PLL designs. In Cadence version 6.x everything works great and there are no problems. Unfortunately, not all of my design kits (I'm working with three different technologies) support the new library format. In Cadence IC 5.1.41 I have the problem that the template does not provide a sweep for the tuning voltage. I can sweep both VDD and VSS, but there is no option to sweep Vtune. My configuration is IC 5.1.41 and MMSIM 7.0. Can anybody tell me if there is possibly something wrong with my setup or if there is a way to manually sweep Vtune and still have the oscillator model generated automatically?

Thanks in advance,
Jens